Routing Congestion in VLSI Circuits: Estimation and Optimization
With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judic
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Series on Integrated Circuits and Systems Series Editor:
Anantha Chandrakasan Massachusetts Institute of Technology Cambridge, Massachusetts
Routing Congestion in VLSI Circuits: Estimation and Optimization Prashant Saxena, Rupesh S. Shelar, Sachin Sapatnekar ISBN 978-0-387-30037-5, 2007 Ultra-Low Power Wireless Technologies for Sensor Networks Brian Otis and Jan Rabaey ISBN 978-0-387-30930-9, 2007 Sub-Threshold Design for Ultra Low-Power Systems Alice Wang, Benton H. Calhoun and Anantha Chandrakasan ISBN 978-0-387-33515-5, 2006 High Performance Energy Efficient Microprocessor Design Vojin Oklibdzija and Ram Krishnamurthy (Eds.) ISBN 978-0-387-28594-8, 2006 Abstraction Refinement for Large Scale Model Checking Chao Wang, Gary D. Hachtel, and Fabio Somenzi ISBN 978-0-387-28594-2, 2006 A Practical Introduction to PSL Cindy Eisner and Dana Fisman ISBN 978-0-387-35313-5, 2006 Thermal and Power Management of Integrated Systems Arman Vassighi and Manoj Sachdev ISBN 978-0-387-25762-4, 2006 Leakage in Nanometer CMOS Technologies Siva G. Narendra and Anantha Chandrakasan ISBN 978-0-387-25737-2, 2005 Statistical Analysis and Optimization for VLSI: Timing and Power Ashish Srivastava, Dennis Sylvester, and David Blaauw ISBN 978-0-387-26049-9, 2005
Prashant Saxena Rupesh S. Shelar Sachin S. Sapatnekar
Routing Congestion in VLSI Circuits Estimation and Optimization
Prashant Saxena Synopsys, Inc. Hillsboro, OR, USA Rupesh S. Shelar Intel Corporation Hillsboro, OR, USA Sachin S. Sapatnekar University of Minnesota Minneapolis, MN, USA Routing Congestion in VLSI Circuits: Estimation and Optimization Library of Congress Control Number: 2006939848 ISBN 978-0-387-30037-5 ISBN 0-387-30037-6
e-ISBN 978-0-387-48550-8 e-ISBN 0-387-48550-3
Printed on acid-free paper. c 2007 Springer Science+Business Media, LLC All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now know or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed in the United States of America. 9 8 7 6 5 4 3 2 1 springer.com
To my parents Kailash and Savitri, and my wife Priti. – Prashant To my mother Keshar and siblings Sandhya and Tushar, and the memories of my father. – Rupesh To my family. – Sachin
Preface
With dramatic increases in on-chip packing densities, routing congestion has become a major problem in integrated circuit design, impacting convergence, performance, and yield, and complicating the synthesis of critical interconnects. The problem is
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