Self-Aligned Formation of C54 Titanium Germanosilicide Using Rapid Thermal Processing and Application to Raised, Ultra-S
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selectively deposited sacrificial layer that can be consumed during solid state silicidation [5-7]. These MOSFET devices with sacrificial source/drain layers are referred to as raised (or elevated) source/drain MOSFETs. In this paper, we propose the use of selectively deposited Sil_"Ge" as a sacrificial layer. Recently, we have demonstrated that Ge and Si1 xGex alloys can be deposited selectively on Si in a cold-walled, rapid thermal chemical vapor deposition system using the thermal decomposition of GeH 4 and SiH 2 Cl 2 [8]. The Sil-xGex alloy can also be implanted or in-situ doped and used as a solid diffusion source for damage-free, ultra-shallow junctions [9, 10]. These aspects make Sil-xGex an excellent candidate to function as a sacrificial layer for solid state metallization in raised junction devices. We present results on solid state reactions between Ti and Sii-xGex alloys. A self-aligned germanosilicide process has been identified and used in the fabrication of raised, ultra-shallow junctions with germanosilicide contacts. Four point probe conductivity/resistivity measurements, x-ray diffraction, and cross-sectional transmission electron microscopy are used to analyze the phase transitions, grain structure and morphology of the reacted materials. Forward and reverse bias current versus voltage characteristics of raised junctions both with and without germanosilicide formation are analyzed and compared to conventional, non-elevated, silicided junctions. EXPERIMENTAL Following an RCA clean and 10 second HF dip, intrinsic and in-situ doped Sii-xGex alloys (approximately 2500 A thick) were deposited onto Si (100) substrates, either patterned with field oxide for device formation, or unpatterned for germanosilicide characterization. Intrinsic wafers were used for germanosilicide characterization and 0.2-0.6 Q-cm n-type or 1-2 Q-cmn p-type wafers were used for device fabrication. Sil-xGex depositions were performed in a LEISKTM cold-walled, rapid thermal processor using 8% GeH4 diluted in H2 , Sil` 2 Cl2 , and H2 . In-situ doping was provided by incorporating B2 H 6 or PH 3 into the gas chemistry. Following these depositions, junctions were formed by diffusion from the Sil-xGex alloys using furnace annealing for p+-n junctions and RTA for n+-p junctions. Diffusions of boron and phosphorus both in and from SiU.Geo.3 alloys have been modeled using SSUPREM4 process simulato~r and Boltzmann Matono analysis [9]. Damage-free, ultra-shallow junctions as shallow as 100 A can be formed using this technique. The Si0 .7 Ge 0 .3 diffusion source was selectively removed from the substrates for the conventional non-elevated, silicided wafers after junction formation [11]. Titanium (300 A thick) was then evaporated onto the substrates in a BALZEDERSTm BAK760 evaporator by resistive heating. The substrates used for germanosilicide characterization were then diced into samples and annealed in a HEATPULSE T " 21lOT Rapid Thermal Annealer. Selfaligned germanosilicide or silicide formation was then performed on the device wafers
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