Short-period (Si 14 / Si 0.75 Ge 0.25 ) 20 Superlattices for the Growth of High-quality Si 0.75 Ge 0.25
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Short-period (Si14/ Si0.75Ge0.25)20 Superlattices for the Growth of High-quality Si0.75Ge0.25 Alloy Layers M.M. Rahman, T. Tambo, and C. Tatsuyama Department of Electrical and Electronic Engineering, Faculty of Engineering, Toyama University, 3190-Gofuku, Toyama 930-8555, Japan ABSTRACT In the present experiment, we have grown 2500-Å thick Si0.75Ge0.25 alloy layers on Si(001) substrate by MBE process using a short-period (Si14/Si0.75Ge0.25)20 superlattice (SL) as buffer layers. In the SL layers, first a layer of 14 monolayers (MLs) of Si (thickness about 20Å) then a thin layer of Si0.75Ge0.25 (thickness 5-6Å) were grown. This Si/(Si0.75Ge0.25) bilayers were repeated for 20 times. The buffer layers were grown at different temperatures from 300-400oC and the alloy layers were then grown at 500oC on the buffer layers. The alloy layer showed low residual strain (about -0.16%) and smooth surface (rms roughness ~15Å) with 300oC grown SL buffer. Low temperature growth of Si in SL layer introduces point defects and low temperature growth of Si1-xGex in SL layer reduces the Ge segregation length, which leads to strained SL layer formation. Strained layers are capable to make barrier for the propagation of threading dislocations and point defect sites can trap the dislocations. INTRODUCTION Despite of low cost, abundant in nature, the process simplicity and prospect of bandgap engineering, SiGe is still away from its full-fledged usages. Due to 4.2% lattice mismatch between Si and Ge, it is difficult to grow high quality Si1-xGex alloy layers. Up to a certain thickness, called a critical thickness, grown Si1-xGex epitaxial layers are pseudomorphic [1-2]. Exceeding of this thickness or annealing the samples at high temperature leads to strain relaxation by introducing a high density of misfit dislocations. Extended part of misfit dislocation which is called threading dislocation can come up to the top of the layer and roughen the top surface. In active devices, these dislocations act like a current leakage path or scattering center for carriers. As a result, the devices with dislocations lose its reliability and perfections, and drastically reduce its performance. Reduction of threading dislocation density along with lower residual strain in the grown layers thus have attracted tremendous attention for the last decades. Thick Si1-xGex layers (several micrometers) are strain relaxed and dislocation densities are also considerably low but thick layers are not good for device fabrications. To achieve dislocation free alloy layers, several types of compensating buffer layers have been used. Among them uniformly graded, step graded Si1-yGey (0≤y≤x) alloy layers [3-4], Si1-yGey superlattices [5], strain balance superlattices [6], strained short-period (Sim/Gen)N superlattices are mentionable [7]. The thickness, density of dislocations, residual strain and surface roughness of various types
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