Growth of high quality Ge epitaxial layer on Si(100) substrate using ultra thin Si 0.5 Ge 0.5 buffer
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0891-EE07-24.1
Growth of high quality Ge epitaxial layer on Si(100) substrate using ultra thin Si0.5Ge0.5 buffer Junko Nakatsuru, Hiroki Date, Supika Mashiro and Manabu Ikemoto Canon ANELVA Corporation, 5-8-1 Yotsuya Fuchu Tokyo 183-8508 Japan,
ABSTRACT As conventional Si based device structures are approaching their physical limits, Ge epitaxial film on Si (100) substrate becomes more attractive for virtual substrates, on which advanced channel engineering techniques to be applied, or integrated Ge photonic devices to be formed. Low threading dislocation density and smooth surface are key features to realize such applications of the Ge/Si virtual substrate. To date, growth methods for Ge epitaxial film on Si (100) substrate involve at least one of thick (micrometer order) SixGe1-x buffer growth process, high temperature annealing steps or Chemical mechanical polishing (CMP) process, any of which could compromise reliability and suitability for production. In this study, feasibility of ultra thin (in the order of 10 nm) SixGe1-x buffer layer for pure Ge epitaxial growth was investigated with regard to Ge layer’s crystallinity, threading dislocation density, and surface roughness, as well as suitability for production. As a result, Ge epitaxial film that has low threading dislocation density with very smooth surface (root mean square (RMS) = 0.44 nm) was successfully grown in shorter process time by using SiGe buffer layer 1/1000 thinner than that of previously known methods without using CMP or high temperature annealing. INTRODUCTION A technique to grow high quality Ge epitaxial layer on Si substrate is indispensable in order to realize Ge photodetectors on Si [1] or Si based high electron mobility devices [2]. Because of the 4.2% lattice mismatch between Ge and Si, however, Ge epitaxial layers on Si (100) have high threading dislocation density (TDD) and surface roughness. Various methods were proposed to realize low TDD and smooth surface. In many cases, completely relaxed, thick graded SixGe1-x layer was used for matching the lattice constant of the underlying layer to that of Ge [3-5]. CMP in combination with thick buffer layer or introduction of high temperature annealing step(s) were also examined of their effectiveness with regard to reducing TDD and surface roughness. Despite of that, such methods typically resulted in TDD in the order of 106 cm-2 and RMS in the order of a few nm. Furthermore, any of thick (micrometer order) SixGe1-x buffer growth process, high temperature annealing steps or CMP process requires long process time or complexity for control, which would work to the disadvantage from manufacturing point of view. In our study, we sought a process that would improve productivity as well as TDD and surface morphology by adopting a thin SixGe1-x layer as a buffer and concentrating stress relaxation on the buffer layer. In order to realize such buffer, 1) The layer should be as thin as possible but to be a continuous film, 2) The layer should have surface roughness of the Si substrate, 3) The lay
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