Silicon Etching Study in a RT-CVD Reactor with the HCl/H2 Gas Mixture
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0910-A24-02
Silicon Etching Study in a RT-CVD Reactor with the HCl/H2 Gas Mixture Nicolas Loubet, Alexandre Talbot, and Didier Dutartre FEOL R&D, STMicroelectronics, 850 rue Jean Monnet, Crolles, 38926, France
ABSTRACT A promising candidate to selectively etch silicon against dielectrics is here studied. This paper reports a detailed study of the silicon chemical vapor etch with HCl/H2 mixtures. Kinetics measurements on (001)-oriented wafers permitted us to extract apparent activation energies varying from 95.2kcal/mol and 73.9kcal/mol, depending on the HCl dilution in the chamber. On the other hand, etch rate measurements as a function of the HCl partial pressure are found to follow a sub-linear behavior indicating complex mechanisms occurring with the use of the HCl/H2 gas mix. In a second part, thanks to SEM cross-section observations, morphological analysis permitted us to point out that the {311} facet behaves differently as compared to the {111} and {100} planes. To conclude, we extracted rugosity data after HCl treatment from Atomic Force Microscopy (AFM) measurements and all these results permitted us to validate the potential industrialization of this etching process for the formation of localized cavities or junctions on patterned wafers. INTRODUCTION The formation of junctions with well-controlled depth and morphology is, today, a key issue in the advanced CMOS engineering. In particular, several studies reported the Source/Drain junction etching and filling with another material than silicon to enhance the carrier mobility in the device channel [1,2]. One of the well-known candidates to etch silicon is the chemical vapor etching with the HCl/H2 mixture. Indeed, the HCl etch process is totally selective against the nitride or oxide dielectrics and allows to form relatively abrupt and highly anisotropic cavities on patterned wafers. Moreover, this method can be performed in any Rapid Thermal Chemical Vapor Deposition (RT-CVD) reactors and, contrary to conventional RIE methods, results in defect-free and chemically pure surfaces. However, the data concerning the HCl etch are rather rare at low temperature. In the past, silicon etch with HCl was extensively studied in the high temperature region (>1000°C) when this precursor was used for surface preparation [3,4]. The HCl/H2 gas mixture is today mainly used to clean chambers of RT-CVD reactors and to ensure a good selectivity during Si or SiGe selective epitaxial growth. In this paper, we report the etch kinetics of the HCl/H2 mixture on blanket wafers, the different etch morphologies obtained on patterned wafers, and also the roughness of etched surfaces as measured by AFM. EXPERIMENTAL DETAILS In this contribution, silicon etch processes were carried out in a 200mm wafer, industrial single wafer RT-CVD reactor from Applied Materials.
For etch kinetics measurements on (001)-oriented blanket wafers, we introduced a SiGe marker below a few hundred nanometers-thick silicon film in order to determine accurately the silicon consumption using Spectroscopical
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