Three-dimensional hybrid bonding integration challenges and solutions toward multi-wafer stacking
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Prospective Article
Three-dimensional hybrid bonding integration challenges and solutions toward multi-wafer stacking L. Arnaud, C. Karam, N. Bresson, C. Dubarry, S. Borel, M. Assous, G. Mauguen, F. Fournel, M. Gottardi, T. Mourier, S. Cheramy, and F. Servant, University Grenoble Alpes, CEA LETI, Grenoble F-38000, France Address all correspondence to L. Arnaud at [email protected] (Received 2 July 2020; accepted 23 September 2020)
Abstract Recent applications require vertical chip stacking to increase the performance of many devices without the need of advanced node components. Image sensors and vision systems will embed more and more smart functions, for instance, image processing, object recognition, and movement detection. In this perspective, the combination of Cu-to-Cu direct hybrid bonding technology with Through-Silicon-Via (TSV) will allow 3D interconnection between pixels and the associated computing and memory structures, each function fabricated on a separate wafer. Wafer-to-wafer hybrid bonding was achieved with multi-pitch design—1–4 μm—of single levels of Cu damascene patterned on 300 mm silicon substrates. Defect-free bonding, as far as the extreme edge of the wafer, was demonstrated on a stack with three wafers. Middle wafers thinning was done with grinding only and with a thickness uniformity (TTV)
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