Silicon-on-lnsulator Technology: Past Achievements and Future Prospects
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diameter of the silicon wafer ranges from 10 cm to 20 cm, and the thickness of the silicon layer is typically only a fraction of a micrometer.. Ideally both the silicon layer and the oxide layer should be defect-free, stressfree, and uniform in thickness, and should display good interface properties. Siliconon-insulator materials produced during the "heroic period" of the early 1980s were full of defects and stress, and were highly uniform in thickness. Early materials were produced by melting and recrystallization of a polycrystalline silicon layer using a laser or a focused halogen lamp (zone-melting-and-recrystallization [ZMR] process).3 It was not totally uncommon to see wafers coming out of the ZMR apparatus as warped as potato chips. Another fabrication technique was based on the formation of a layer of porous silicon and the oxidation of this layer. This technique was unfortunately just as capable of yielding potato-chip-shaped wafers as ZMR was. Other techniques made use of lateral epitaxial growth of silicon over SiO2 or the slow recrystallization of amorphous silicon deposited on an insulator. Although interesting materialscience problems were tackled during these early years of SOI research and even though some significant SOI and threedimensional circuits were fabricated using these materials, all of these fabrication methods have virtually been replaced by a few more successful competing techniques. Three techniques for producing SOI material have emerged and have made it to the stage of commercialization. They are as follows:
• The separation-by-implantation-of oxygen (SIMOX) technique in which oxygen ions are implanted into a silicon wafer in order to synthesize a buried oxide layer underneath a thin silicon overlayer. • The bonding-and-etched-back-SOI (BESOI) technique in which two oxidized silicon wafers are mated and bonded. One of these wafers is then polished back and thinned to form a thin SOI layer. • The Smart Cut® process in which ion implantation is used to cut off a thin silicon layer from a silicon wafer and bond it onto another wafer. The SOI material produced by this technique is called Unibond® material. The quality of modern, commercially available SOI substrates is quite excellent. The density of dislocations found in the silicon overlayer in SIMOX wafers was exceeding 1 X 107cm2 in 1985. In 1998 that density has been reduced to a few thousands of dislocations per square centimeter in standard material. Defect densities comparable to bulk silicon can be found in advanced, low-dose SIMOX wafers. This decrease of defect density makes it possible to fabricate ultralargescale-integration circuits such as large dynamic random-access memories (DRAMs) (e.g., 1-Gb DRAM reported by Hyundai in 1997).4 Separation-by-implantation-of-oxygen and Unibond® wafers produce wafers in which the silicon-film thickness and the buried oxide thickness are typically 200 nm and 400 nm, respectively. Variations of the fabrication parameters (such as implantation dose and energy) can however provide other fi
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