Silver Damascene Process with Cap Layer
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Silver Damascene Process with Cap Layer Masahiro Ota1, Manabu Tsujimura2, Hiroaki Inoue2, Hirokazu Ezawa3 and Masahiro Miyata 3 1
Department of mechanical engineering, graduate school of eng. Tokyo Metropolitan University 1-1, Minami-Oosawa, Hachi-oji, Tokyo, Japan 2 Precision Machinery Group, Ebara Corporation 5-37-1 Kamata Ohta-ku Tokyo Japan 3 Toshiba Corp. Semiconductor Company 8,Shinsugita-cho, Isogo-ku, Yokohama, Japan ABSTRACT Development of semiconductors has proceeded according to broad frameworks such as the International Technology Roadmap for Semiconductors (ITRS). A key development in semiconductor technology involves the adoption of several new materials, such as Cu, low-k and high-k materials, and noble metals in capacitors, transistors, and/or interconnects. These developments will likely lead to wider application of the planarization process to new processes and new materials, and call for even stricter planarization performance requirements. One example involves planarizing Ag interconnects with an optimal cap layer configuration for reducing RC delays. The Cu interconnect process is currently used to reduce wire resistivity. One material that has been proposed as a successor to Cu is Ag. Many low-k materials have been developed with the goal of reducing dielectric constant (k). However, damascene design and matters such as cap layer configuration are also important considerations in reducing the effective dielectric constant (k eff). Our report herein begins by proposing Ni-B deposited by electroless plating as a candidate cap material, due to the following characteristics: (1) it offers good selectivity for Ag interconnects; (2) it provides good barrier effects through thermal processes; and (3) it provides good controllability of deposition rates. Next, we report that Ag damascene with Ni-B cap layer can be realized through electroplating and polishing of Ag interconnects. Although Ag polishing technologies are currently not fully developed, we suggest that they may nevertheless be successfully applied to polish Ag. INTRODUCTION As discussed in the International Technology Roadmap for Semiconductors (ITRS), the history of semiconductor devices is characterized by two trends: finer node scaling and larger wafer-size scaling. In technical nodes after the 130 nm node, Cu and/or low-k materials are generally selected as materials to reduce RC delays, and electrochemical plating is adopted for metallization of Cu interconnects. However, cap layers and their design configurations are also important factors in reducing the effective dielectric constant (k). CMP has been adopted in several processes, including ILD, W-plug, STI, Cu/low-k processes and so on. In this report, cap-layer issues for Ag are reported first 1), followed by a report on silver damascene interconnects with a cap layer by CMP.
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