Spectroscopic Ellipsometry for Inline Process Control in the Semiconductor Industry
Building high-performance silicon CMOS or III/V devices requires many structural process steps, where a physical layer (dielectric, epitaxial semiconductor, gate electrode, or metal contact) is first deposited across the wafer and then partially removed b
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Spectroscopic Ellipsometry for Inline Process Control in the Semiconductor Industry Stefan Zollner
Abstract Building high-performance silicon CMOS or III/V devices requires many structural process steps, where a physical layer (dielectric, epitaxial semiconductor, gate electrode, or metal contact) is first deposited across the wafer and then partially removed by a masked or blanket etch process. Whenever possible, the deposition and etch processes are verified by a thickness metrology step. Typically, a latest-generation CMOS process flow contains about 100 thickness measurements, at least during the development of the technology. The metrology method of choice in the semiconductor industry is spectroscopic ellipsometry, because it is fast, nondestructive, and capable of measuring product wafers in small areas (30–50 µm beam diameter) set aside in the scribe grid. This chapter will describe several typical applications of ellipsometry in CMOS and III/V device manufacturing and address capabilities and limitations and how future basic research on optical properties of materials can benefit the industry.
18.1 Introduction Building a high-performance complementary metal-oxide-semiconductor (CMOS) processor (see Fig. 18.1) with eleven layers of metals requires about 75 photolayers [9]. Many of these are dopant implant layers and therefore only require after develop inspection (ADI), overlay, and critical dimension (CD) metrology for optical lithography. However, there are about 40 structural process steps, where a physical layer (dielectric, epitaxial semiconductor, gate electrode, or metal contact) is first deposited across the wafer and then partially removed by a masked or blanket etch process (wet or dry). Whenever possible, the deposition and etch processes are verified by a thickS. Zollner (B) Department of Physics, New Mexico State University, MSC 3D, P.O. Box 30001, Las Cruces, NM 88003-8001, USA e-mail: [email protected] M. Losurdo and K. Hingerl (eds.), Ellipsometry at the Nanoscale, DOI: 10.1007/978-3-642-33956-1_18, © Springer-Verlag Berlin Heidelberg 2013
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Fig. 18.1 Left transmission electron micrograph (TEM) of an N-channel metal-oxide-semiconductor (NMOS) field effect transistor. In the center of the image, from the bottom, we see the transistor’s Si channel (grey), followed by the metal oxide gate dielectric as a thin bright line, a dark transition metal nitride acting as the thin metal gate, followed by a polycrystalline silicon gate (grey), then the dark NiSi gate electrode contact. The gate is encapsulated on both sides by a thin nitride spacer (grey), a thin L-shaped oxide spacer (bright), and a final nitride spacer (grey). Above the gate, we see the dual stress nitride liner etch stop (grey). On both sides, there are tungsten plugs (dark) with transition metal nitride barriers (not visible) landing on the NiSi contacts to the silicon current electrodes. PMOS devices are similar, but have silicided Si1−x Gex source-drain stressors. c 2009 The Japan Society The gate width of t
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