Stress Characterization of Post-CMP Copper Films Planarized Using Novel Low-Shear and Surface-Engineered Pads
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Stress Characterization of Post-CMP Copper Films Planarized Using Novel Low-Shear and Surface-Engineered Pads Manish Deopura,1, 2, a Edward Hwang,1 Sudhanshu Misra,1 and Pradip K. Roy1 1 Neopad Technologies Corporation, Sunnyvale, California, USA 94085 2 Department of Materials Science and Engineering, Massachusetts Institute of Technology 77 Massachusetts Avenue, Cambridge, Massachusetts, USA 02139 a
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ABSTRACT A family of novel low-shear and surface-engineered pads for copper chemical mechanical planarization (CMP) are designed and evaluated for polishing characteristics and process induced stress. Tribological studies are carried out on blanket copper films using these low-shear/surface-engineered pads and comparison is made with state of the art commercial pads (IC1000 and JSR). Results indicate that low-shear surface-engineered pads exhibit vastly improved tribological performance. These pads exhibit a 40% lower coefficient of friction (COF) over a larger range of Sommerfeld numbers (So) compared to commercial pads. A simplified XRD line profiling technique has been utilized to characterize stress within post-CMP copper films. The (222) Bragg peak position obtained from the XRD spectra of films polished using low-shear surface-engineered pads indicates virtually no shift compared to the peak position for the unpolished copper films. This result establishes that almost no stress is incorporated during bulk Copper removal using the newly designed pads. INTRODUCTION Copper is rapidly replacing aluminum in advanced integrated circuits due to its lower resistivity and better electro-migration resistance [ 1 ]. As the technology node is lowered, especially below sub-90nm, the use of Cu/low-k interconnects becomes more critical for devices [ 2 ]. The sub-90nm Cu/low-k interconnect technology allows for increased device speed, enhanced electro-migration resistance and improved scalability. Fabrication of integrated circuits at these technology nodes using the Cu/low-k materials combination has several challenges associated with it. The most prominent amongst these challenges is the design of an efficient chemical mechanical planarization (CMP) process which is required at each level of interconnect metallization [3]. The process of copper metallization involves several steps [4]. The first step involves etching of the blanket dielectric (oxide) films to create trenches and vias. After barrier layer deposition, these trenches and vias are filled by electrochemical deposition of copper. Electrochemical deposition is not often uniform. Higher pattern density areas tend to fill up quicker compared to bond pads or other lower pattern density areas. In the next step of Chemical Mechanical Planarization (CMP), the excess copper is removed so that the inlaid copper lines end up flush with (or slightly recessed from) the oxide surface. The CMP process must clear areas with a heavy copper overburden, while not damaging other areas. Line resis
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