Stress evolution in integrated SrBi 2 Ta 2 O 9 ferroelectric layers
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Stress evolution in integrated SrBi2Ta2O9 ferroelectric layers J.G. Lisoni1, K. Wafer1, J.A. Johnson1, L. Goux1, M. Schwitters1, V. Paraschiv1, D. Maes1, L. Haspeslagh1, C. Caputa2, R. Zambrano2 and D.J. Wouters1 1 IMEC, Silicon Process and Technology Devices Division, Leuven-Belgium 2 STMicroelectronics, MPG Devt Center Catania, Catania-Italy ABSTRACT In our integration scheme, a “pseudo-3D” capacitor cell is used where the TiAlN\Ir\IrO2\Pt bottom electrode is patterned before SBT deposition. In order to understand how this system behaves mechanically, we have investigated the evolution of the stress of blanket Sr1-xBi2+yTa2O9 (x, y < 0.5) layers deposited on this pre-patterned bottom electrode stack. SBT was deposited by metal organic vapor deposition (MOCVD) between 405 °C and 440 °C. The stresses were monitored by the change in the radius of curvature of the wafer at the subsequent processing steps: deposition of electrodes and SBT, crystallization and recovering annealing, and after removal of Pt top electrode, SBT and bottom electrode layers by dry etching. The stress conditions observed for the different planar layers as a function of the SBT deposition temperature was correlated to the TiAlN lateral oxidation length observed in the etched structure after the SBT crystallization step.
INTRODUCTION The integration of ferroelectric materials with silicon technology requires complex barrier layer schemes, whose combined stresses determine the mechanical stability of the system. Currently, for high-density ferroelectric memories (FeRAM’s), all cell designs are based on 2D capacitors [1]. In that case, the blanket electrodes are etched together with the ferroelectric film in one single step. However, for the future generations compatible with C0090 or more advanced CMOS technologies, a 3D design will be required in order to gain polarization signal from the sidewalls of the ferrocapacitors. Our current approach is a “pseudo-3D” SrBi2Ta2O9-based (SBT) capacitor stacked on top of W plugs (Figure 1). First, the bottom electrode (BE), TiAlN\Ir\IrO2\Pt, is patterned. Then, SBT is deposited and crystallized at 700 °C, exposing the top part and the sides of the open electrode to the oxidizing atmosphere (Figure 1). It has been already demonstrated that the BE aforementioned is a good oxygen barrier in the normal direction and mechanically stable when blanket layers are annealed at the SBT anneals conditions [2]. However, in open mesas the contact resistance is endangered mainly due to the TiAlN lateral oxidation, while Pt and IrO2 are thermally stable at these annealing conditions. In particular, it should be avoided that this lateral oxidation is larger than the overlap distance between the electrode and the W plug. For Ir, a selflimiting iridium oxide layer is formed without any abrupt change in the volume of the layer. In the case of blanket TiAlN layers, also a self-limiting oxide layer is grown [3]. It is known that Al diffuses to the surface of the film and oxidizes leaving in the bulk the remaining conduc
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