Stressmigration Behavior of Multilevel Ulsi Alcu-Metallizations
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STRESSMIGRATION BEHAVIOR OF MULTILEVEL ULSI ALCU-METALLIZATIONS A.H. Fischer, A.E. Zitzelsberger, M. Hommel and A. von Glasow Infineon Technologies AG, Reliability Methodology, Munich, Germany ABSTRACT With decreasing geometries of metal interconnects the demands on metallization reliability increase rapidly. In addition to electromigration, stress-induced voiding becomes a major problem, influencing lifetime and functionality of integrated circuits. This paper summarizes our studies on stressmigration behavior of various AlCu-multilevel metallizations. A model for an estimation of the median time to failure is presented. INTRODUCTION In reliability methodology stress-induced voiding is an issue of intensive discussion, due to the complexity of physical mechanisms acting in thin metal films and narrow interconnect lines during development and relaxation of mechanical stress. Many efforts were done in order to estimate the stressmigration-limited lifetime of ULSI AlCu-metallizations [1,2,3]. However, the assessment of the stressvoiding problem in process qualification often has a more qualitative character: Avoid the occurrence of stress-induced voids for high performance applications! Three basic stressmigration-related risks can be distinguished. The primary risk is an increase in line resistance because of stress voids, affecting the circuit functionality. It can probably be controlled by providing a model which allows, similar to Black’s equation for electromigration, the transformation of the failure distribution from highly accelerated to operation conditions. The secondary risk is the influence of stress voids on the electromigration (EM) performance. If the EM-failure is due to the growth of pre-existing voids, the current density exponent in Black's equation will be close to one [4] and as a consequence a lower EM-lifetime is obtained [5]. A third risk is conceivable due to the statistical nature of stress-void formation. Here, stressvoiding in narrow or short lines and at vias may cause higher resistances, early fails or weak links. This paper will focus on the primary risk from the viewpoint of process qualification, where stressmigration monitoring is in general limited to resistance drift measurements after high temperature storage. Methods which otherwise allow the direct measurement of stress (e.g. X-ray diffraction), are unsuitable for this purpose. Stress relaxation in interconnect lines during high temperature storage (HTS) In the following a simplified scenario is considered to estimate the stressmigration mean time to failure. Due to the thermal mismatch between metal line, substrate and encapsulating oxide, a tensile stress is obtained at the interconnect during cooldown from high deposition temperatures. This thermally-induced stress can be expressed by: σ 0 = E eff ∆α (Tdep − Tstr ) (1) where Tdep is the deposition temperature of the dielectric, Tstr the storage temperature, Eeff the appropriate elastic modulus and ∆α the difference in thermal coefficients of expansion between metal and surround
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