Design and Analysis of IGZO Based Junctionless Thin Film Transistor Using SOI Technology
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ORIGINAL PAPER
Design and Analysis of IGZO Based Junctionless Thin Film Transistor Using SOI Technology Rahul Prakash Singh 1
&
Mamta Khosla 2 & Indu Saini 2 & Naveen Kumar 1
Received: 12 July 2020 / Accepted: 26 October 2020 # Springer Nature B.V. 2020
Abstract In this paper, IGZO based Junctionless Thin Film Transistor (IGZO JLTFT) using SOI technology is proposed with a channel length of 20 nm. The article also demonstrates a comparative analysis of amorphous Silicon-based JLTFT and artificial material IGZO based JLTFT using the Silvaco Atlas tool. Based upon the Junctionless properties, the compound, and high bandgap material, Indium Gallium Zinc Oxide (IGZO) is used to overcome the Short Channel Effects (SCEs) caused due to continuous miniaturization of the channel size. Optimization of the proposed SOI based IGZO JLTFT device has been carried out, by varying the Buried oxide and gate oxide materials and their thicknesses, and HFO2 has been demonstrated to give the best Ion/Ioff ratio. Further, gate metal work-function engineering is employed to enhance the performance of the proposed device in terms of increasing on-state current, and reducing off-state current. Through rigorous simulations with variations in different device parameters, it is demonstrated that the 20 nm IGZO JLTFT with HfO2 as Buried and Gate oxides, and work functions of 4.8 eV each for both metal gates, provides the best performance such as: Ioff of 9.97*10−12 A, threshold voltage of 0.38 V, overall gate capacitances of 1.13*10−15 F, and Subthreshold Slope (SS) of 93 mV/dec. Keywords Junctionless thin film transistor (JLTFT) . Indium gallium zinc oxide (IGZO) . Silicon on insulator (SOI) Technology . Subthreshold slope (SS)
1 Introduction Over the past six decades, MOSFETs have been extremely important in exploring new frontiers in low power devices for analog applications. The continuous down scaling of MOSFETs has led to miniaturization of devices along with increased speed and functionality. However, poor scaling * Rahul Prakash Singh [email protected] Mamta Khosla [email protected] Indu Saini [email protected] Naveen Kumar [email protected] 1
VLSI Lab, National Institute of Technology Jalandhar, Jalandhar, India
2
Department of Electronics and Communication Engineering, National Institute of Technology Jalandhar, Jalandhar, India
properties of MOSFET have failed to meet today’s technological demands [1]. The main problems associated with the scaling are Short Channel effects (SCEs) such as degradation in mobility, threshold voltage variation, increase in OFF current (IOFF) and difficulty in increasing of ON current (ION) [2]. Several techniques such as dual work function Gate, shallowing of the channel, heteromaterial, and varying oxide dimensions and materials have been used to reduce the gate leakage and SCEs [3–8]. Dual work function Gate improved the current driving capabilities of the device and hence reduced major SCEs like Drain-induced barrier lowering (DIBL) as well as Hot Carrier Effect (HCE) [3–5]. Higher die
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