Study of Fatigue Behavior of 300 nm Damascene Interconnect Using High Amplitude AC Tests*
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0990-B09-09
Study of Fatigue Behavior of 300 nm Damascene Interconnect Using High Amplitude AC Tests* David Read1, Roy Geiss1, and Glenn Alers2 1 National Institute of Standards and Technology, Boulder, CO, 80305 2 University of California at Santa Cruz, Santa Cruz, CA, 95064
ABSTRACT The AC fatigue test technique, which uses cyclic joule heating to apply thermal cycles to thin-film structures, was applied to copper lines and vias in damascene dielectric structures on silicon substrates. Specimen chips with two different types of dielectric, oxide and low-k, were tested. The lines were 300 nm wide; various via widths were tested. At 100 Hz, cyclic temperature ranges from 400 to 900 ∫C produced line lifetimes between 10 and 1 million seconds. Similar lifetimes were reached in the vias for temperature ranges between 100 and 500 ∫C. When the data were plotted either as number of load reversals to failure or as lifetime against cyclic temperature range, the trends for the two different types of dielectric were indistinguishable. The temperature values at the one-reversal intercept for both types of dielectric were above 1000 ∫C. The via data were more scattered, but trended toward a lower intercept temperature. INTRODUCTION Along with billions of transistors, the ultra large scale integration logic chips in the current generation contain billions of individual ìinterconnectsî, which are copper conductors connecting different transistors and other components within a chip. The reliability of these interconnects is critical because a single failure can render the whole chip inoperative. Stresses in the interconnect system are created during manufacture by chemical-mechanical polishing and annealing cycles up to around 400 ∫C, and during service by both on-off and idle-active thermal cycles of tens of degrees Celsius. Clearly, the idle-active cycle can occur many times per day. Efficient design implies minimization of the physical size of the whole interconnect structure, while maintaining electrical performance and reliability. The mechanical characteristics of the interconnect system define its reliability against stresses from all sources, most importantly, against thermomechanical stresses. The AC fatigue test technique [1] uses cyclic Joule heating to apply thermal cycles to metal lines and vias in damascene dielectric structures on silicon substrates. Cyclic stresses from differential thermal expansion produce elastic and possibly plastic deformation in the metal line and its surrounding dielectric. The use of high-amplitude, low-frequency alternating current in tests of thin-film copper lines was explored by Mˆnig et al. [1]; they reported surface topography changes that appeared to be mechanical in origin. Tests of aluminum lines under by AC fatigue produced topographic damage in the form of regular undulations or wrinkles [2].
*Contribution of the U. S. Department of Commerce, National Institute of Standards and Technology. Not subject to copyright in the U.S.
Extensive transmission electron microscopy (TEM)
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