Fatigue of Damascene Copper Lines under AC Loading
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Fatigue of Damascene Copper Lines under AC Loading Stéphane Moreau1, Sylvain Maitrejean1, and Gérard Passemard2 1 D2NT/LBE, CEA-LETI MINATEC, 17 avenue des Martyrs, Grenoble, France, Metropolitan 2 STMicroelectronics, 850 rue Jean Monnet, Crolles, France, Metropolitan ABSTRACT Fatigue in damascene copper line has been investigated by using alternating currents to generate cyclic temperatures and stresses/strains. Interconnects using beyond 65 nm node design rules and materials have been studied. We demonstrate that cyclic thermal strains lead to Cu or Cu/Co-based cap surface modification and open circuits in Cu lines during the application of an alternating electrical current. We underline that the narrower the copper lines are, the more reliable they are and the major role of the cap layer to improve the Cu lines reliability. Moreover, a statistical approach is presented in this paper in order to discuss about the thermal fatigue associated distribution model (exponential, lognormal and Weibull distributions). At present, the lognormal distribution seems to be the most appropriate one. INTRODUCTION As feature sizes for advanced IC technology continue to shrink, Cu/Ultra Low K (ULK) interconnect technology provides solutions to reduce cross-talk, power consumption and improve overall device performance. In return, interconnects are subjected to increasing current densities because constant current/voltage levels are used [1]. Thus, interconnects experience harsh conditions like high temperatures, high current densities and large thermal strains not only during their manufacturing (film deposition, annealing…) but also during their use (power cycling, energy-saving, processor-intensive usage…). Consequently, three principal wearouts can affect interconnects reliability: ElectroMigration (EM), Stress-Induced Voiding (SIV) and thermal fatigue. Both EM and SIV had been actively investigated since the late 60’s when the first integrated circuits became commercially available [2]. Thermal effects and the associated phenomenon, thermal fatigue, will arise when interconnects are subjected to a periodic voltage signal. Joule effect will create temperature variations repeatedly and due to the coefficients of thermal expansion mismatch, mechanical stresses will appear in the structure. Thermal fatigue was first reported in 1971 by Philofsky et al. [3] but was really tackled since 2002 [4] by the NIST (USA) and the Max-Planck-Institut (Germany). It was observed that thermal fatigue damage also forms in aluminum and copper interconnections for smaller dimensions [4-6]. Moreover, they have demonstrated, with a special test structure, that thermal fatigue phenomenon is not hidden electromigration [5]. The damage observed in their experiments is due to thermal fatigue and not to electromigration-induced atom transport. The intent of this paper is to assess how realistic thermal fatigue may be a reliability threat for dual damascene copper interconnects of the 65 nm technology node and beyond. The focus of this paper is
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