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J.M. Finder and J. Wang Physical Science Research Laboratories, Motorola Inc., Tempe, Arizona 85284

Z.L. Wang School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332-0245

Z. Yu, J. Ramdani, R. Droopad, and K.W. Eisenbeiser Physical Science Research Laboratories, Motorola Inc., Tempe, Arizona 85284

R. Ramesh Materials Research Science and Engineering Center, University of Maryland, College Park, Maryland 20742 (Received 26 February 2001; accepted 31 October 2001)

Microstructure in the SrTiO3/Si system has been studied using high-resolution transmission electron microscopy and image simulations. SrTiO3 grows heteroepitaxially on Si with the orientation relationship given by (001)STO //(001)Si and [100]STO //[110]Si. The lattice misfit between the SrTiO3 thin films and the Si substrate is accommodated by the presence of interfacial dislocations at the Si substrate side. The interface most likely consists of Si bonded to O in SrTiO3. The alternative presentation of Sr and Si atoms along the interface leads to the formation of 2× and 3× Sr configurations. Structural defects in the SrTiO3 thin film mainly consist of tilted domains and dislocations.

I. INTRODUCTION

There is now a considerable effort aimed at the deposition of SrTiO3 (STO) dielectric thin films on silicon substrates since SrTiO3 is an alternative to silica (SiO2) as the gate dielectric in a field effect transistor.1–9 SiO2 has been used as the gate dielectric in a field effect transistor since the 1960’s. However, SiO2-based transistor technology is approaching its fundamental limits: as the SiO2 thickness scales below 2 nm the gate leakage of the metal oxide semiconductor field effect transistor will become unacceptably high due to excessive tunneling current. Technology road maps for the semiconductor industry predict the need for 2 nm and below gate dielectrics in the near future. A systematic consideration of the required properties of gate dielectric indicates that the key guidelines for selecting an alternative gate dielectric are dielectric constant k, conduction band offset to silicon ⌬EC, interface quality between the gate dielectric and the silicon substrate, film morphology, thermodynamic stability, reliability, etc.10 Possible alternative gate 204

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J. Mater. Res., Vol. 17, No. 1, Jan 2002 Downloaded: 26 Mar 2015

dielectrics investigated are Ta2O5,11–13 TiO2,14 ZrO2,15 ZrSixOx,16 HfSixOx,17 and SrTiO3.1–9 The novel gate oxides must be either epitaxially grown or amorphous to avoid unacceptable scatter of the properties due to granularity effects. Among the reported high-k materials,1–17 perovskite-type SrTiO3 lends itself as one of the most promising candidates for alternative gate oxide with desirable structural and dielectric properties. Although the reported conduction band offset value for the SrTiO3–Si system is relatively low (⌬EC < 0.5 eV), which would lead to high leakage current,10,20 high-quality epitaxy SrTiO3 films grown on silicon substrate are expect