Study of SrTiO3 Gate Dielectrics
- PDF / 427,741 Bytes
- 10 Pages / 612 x 792 pts (letter) Page_size
- 77 Downloads / 224 Views
0966-T12-04
Study of SrTiO3 Gate Dielectrics C.Y. Liu1 and Tseung-Yuen Tseng2 1
Department and Institute of Electronic Engineering, National Kaohsiung University of Applied Sciences, Kaohsiung, 807, Taiwan 2
Department of Electronics Engineering, National Chiao Tung University, 1001 Ta Hsueh Road, Hsinchu, 300, Taiwan ABSTRACT Among various possible candidates of high-k gate dielectrics, SrTiO3 plays an important role because it has high dielectric constant and it can be epitaxially grown on silicon substrate. The fabrication process and properties of SrTiO3 gate dielectrics are reported. The effect of the addition of SiO2 on the microstructure and electrical properties of SrTiO3 gate dielectric is also presented. The minimization of the effect of interfacial layer between SrTiO3 and Si is the most important issue for obtaining high quality high-k gate dielectrics. The possible methods to improve the interfacial properties and the measurement techniques to characterize the interfacial layer are discussed. INTRODUCTION In the past several decades, the device scaling is the main driving force for the semiconductor industry. The device scaling would increase the driving current and packing density. Following the device scaling, the gate dielectric is also needed to be thinner leading to increase the driving current and reduce short channel effect. However, the leakage current of the gate dielectric increases with a decrease in thickness of the gate dielectric, which is due to the direct tunneling mechanism. While the gate dielectric is thinner than 3 nm, the leakage current density increases one order of magnitude for every 0.2 nm decrease in SiO2 thickness, which is not acceptable while the SiO2 is less than 2 nm in the future generation [1]. The large leakage current would degrade the device performance and lead to large power consumption. The tunneling current is due to the quantum mechanics, which is a physical limit for the device scaling. In addition, ultrathin SiO2 film would also lead to many issues such as reliability, ultrathin oxide breakdown, oxide uniformity, boron penetration, surface preparation, and rapidly increasing electric field across the gate dielectric. Therefore, other materials should be adopted to replace SiO2 as gate dielectrics. The criteria for selecting an alternative gate dielectric include
permittivity, band gap, band alignment to silicon, thermal stability on silicon, film morphology, interfacial quality, process compatibility, and reliability [2]. The main issue of SiO2 gate dielectric is high leakage current density due to the direct tunneling. The high-k materials can have the same capacitance with larger physical thickness to prevent the direct tunneling. The capacitance of materials can be expressed as equivalent oxide thickness (EOT).
EOT =
ε SiO A 2
C
=
ε SiO A 2
ε high − k t high − k
(1)
where ε SiO2 is the permittivity of SiO2, A the area, C the capacitance, ε high − k the permittivity of high-k material, and thigh − k the thickness of high-k material. Many materia
Data Loading...
