Linear Distortion Analysis of 3D Double Gate Junctionless Transistor with High-K Dielectrics and Gate Metals
- PDF / 2,130,275 Bytes
- 8 Pages / 595.276 x 790.866 pts Page_size
- 63 Downloads / 231 Views
ORIGINAL PAPER
Linear Distortion Analysis of 3D Double Gate Junctionless Transistor with High-K Dielectrics and Gate Metals Achinta Baidya 1
&
T. R. Lenka 2 & S. Baishya 2
Received: 28 March 2020 / Accepted: 24 August 2020 # Springer Nature B.V. 2020
Abstract The paper presents the investigation of linearity distortion analysis of double gate junctionless transistor with high-k gate dielectrics and gate metals. As double gate junctionless transistors have shown high performance in digital circuits, linearity analysis is carried out to understand nonlinear behavior of the device for RFIC applications. In order to ensure minimum intermodulation and higher order harmonics at the system output, different linearity parameters like Second Order Voltage Intercept Point, Third Order distortion, Third Order Input Intercept Point and Third Order Intermodulation Distortion are evaluated. The results show that junctionless transistor should be biased at appropriate low voltage to ensure better linearity which is desired for RFICs. The effects of high-k gate dielectrics and gate metals on linearity characteristics of junctionless transistor are also investigated. Deterioration of the linearity is observed in junctionless transistor for the use of high-k insulators as gate dielectrics. It is also observed that low work function gate material is suitable to achieve higher linearity in low power applications. Keywords Junctionless transistor . Non-linear distortion . VIP2 . VIP3 . IMD3
1 Introduction Continuous effort to get improved performance in integrated circuits sets new stages in semiconductor industry. Downscaling of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices improves packing density, decreases power requirement. It helps to achieve high speed and reduce costs of ICs. But the reduction in size of the devices also contributes to new problems called as short channel effects [1]. New devices and materials are introduced to cope up with these short channel effects. Several channel and gate
* Achinta Baidya [email protected] T. R. Lenka [email protected] S. Baishya [email protected] 1
Department of Electronics and Communication Engineering, Mizoram University, Aizawl 796004, India
2
Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Assam 788010, India
stack engineering techniques are explored to enhance these downsized device performances [2–5]. J. P. Colinge et al. conceptualizes metal oxide semiconductor transistor structure with no junction, which was firstly reported in 2009 [6]. This junctionless transistor conduction mechanism is similar to an accumulation mode transistor and acts like a gated resistor. Investigations in recent years showed that junctionless transistor has advantages over conventional MOSFETs and been projected as an alternative for deep submicron technology [7–11]. Intrinsic strength, ease of fabrication and achievable high packing density make junctionless transistor a candidate for More-than-Moore systems.
Data Loading...
