Supramolecular Approaches to Nanoscale Dielectric Foams for Advanced Microelectronic Devices
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Approaches to Nanoscale Dielectric Foams for Advanced Microelectronic Devices Craig J. Hawker, James L. Hedrick, Robert D. Miller, and Willi Volksen
Introduction The increasing demands of miniaturization in the microelectronics industry has forced continual improvement in the materials that are used in the fabrication of semiconductor devices. Advances in photoresists for microlithographic applications have reduced the feature size to 0.25 m and below, and this drive to eversmaller features, coupled with the introduction of copper, has placed increasing demands on the dielectric material. Materials with lower dielectric constants (depicted in dark gray in Figure 1) are therefore required to more efficiently insulate these submicron features, such as the copper interconnect lines used to connect the transistors and memory cells in these advanced multilevel devices (Figure 1). This allows the minimization of crosstalk, signal delays, and power consumption. While vapor-deposited silicon dioxide and other derivatives are currently being employed, they suffer from unacceptably high dielectric constants ( 3.6) and are unacceptable for future generations of microelectronic devices.1 In order to accommodate all of these requirements and to maximize the performance of devices based on sub-0.18-m lithography and copper metallurgy,2 dielectric materials with 2.0 are required. Arguably the only practical method for
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obtaining such low-dielectric-constant materials is by the controlled incorporation of porosity. Techniques using supramolecular materials allow for the introduction of submicron-sized pores and have shown significant promise in a variety of areas. For example, amphiphilic block copolymers3 and nonionic oligomeric surfactants4 have been used to direct the organization of polymerizing tetraethylorthosilicate (TEOS) and other
Figure 1. Cross-section profile of a six-level chip employing copper metallurgy. The dielectric material is shown in dark gray.
derivatives to produce well-ordered hexagonal mesoporous silica with pore sizes between 75 Å and 300 Å. A critical step in this process is the thermal removal of the templating polymer and retention of the original supramolecular structure. For microelectronic applications, the main problems with these approaches are the significant shrinkage associated with the polymerization of TEOS, its demanding processing requirements, and its high water adsorption. This complicates the development of a manufacturable process for thin-film dielectric materials using TEOS in its present form. However, the powerful nature of this porogen (poregenerating) approach can be appreciated by considering the wide application of this general concept. For example, a similar polymer templating/thermolysis approach has been used to prepare nanoporous gold via the assembly of polystyrene latex microspheres, followed by formation of the surrounding gold matrix and subsequent thermolysis and removal of the polystyrene nanoparticles.5
Block Copolymer Approach Initially, the self-ass
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