Modeling and Fabrication of Cladded Ge Quantum Dot Gate Silicon MOSFETs Exhibiting 3-State Behavior
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1108-A05-04
Modeling and Fabrication of Cladded Ge Quantum Dot Gate Si MOSFETs Exhibiting 3-State Behavior F. C. Jain1, M. Gogna1, F. Alamoody1, S. Karmakar1, E. Suarez1, J. Chandy1, and E. Heller2 1 Department of Electrical & Computer Engineering, University of Connecticut, Storrs, CT 06269; 2RSoft Design Group, Ossinings, NY 10562 ABSTRACT This paper presents electrical transfer (Id-Vg) and output (Id-Vds) characteristics of a GeOx-cladded-Ge quantum dot (QD) gate Si MOSFET devices. In QD gate FETs, the manifestation of an intermediate state ‘i” makes it a 3-state device. The intermediate state originates due to compensation of increment in the gate voltage by a similar increase in the threshold voltage, which occurs via charge neutralization in the QD gate due to transfer of charge from the inversion layer to either first or second of the two QD layers. INTRODUCTION Quantum dot (QD) gate memories have been fabricated in a number of ways since the first reporting by Tiwari et al. [1]. During the fabrication of self-assembled SiO2-cladded Si quantum dot nonvolatile memories, it was observed that QD gate FET structures (without control insulator layer and having two layers of cladded QDs) exhibit a novel intermediate state ‘i’ in the transfer (drain current Id-gate voltage Vg) characteristics, not observed in conventional FETs [2]. That is, the transfer characteristics show three stable states ("0", "1" and "i"), where the lowcurrent saturation state "i" is manifested over a range of gate voltages which is determined by the gate insulator properties (e.g., thickness and energy gap) and the composition of cladded QDs. This paper presents observation of 3-state behavior in the transfer and output characteristics of GeOx-cladded-Ge quantum dot gate Si MOSFETs. Similar to SiOx-Si QD gate Si FETs, here an increase in gate voltage (beyond the threshold voltage VTH1) is compensated by an increase in the effective threshold voltage via charge neutralization in the QD gate, resulting in an intermediate state ‘i’. In addition, capacitance-voltage behavior recently observed in some GeOx-cladded-Ge quantum dot gate Si MOS capacitors that distinctly show two threshold regimes (that is, a step in the capacitance plot) corresponding to presence of an intermediate state. This results in a novel plateau in the C-V behavior. The 3-state FETs can be used for analog and digital circuits including multiple-valued logic (MVL) [3], and our group has recently reported [4] simulations on MVL. THEORY AND EXPERIMENT Theory The intermediate state “i” in SiOx-Si QD gate Si FETs [2] was explained using a model that self-consistently solves Schrödinger and Poisson equations with built-in transfer of carriers from the inversion channel to two layers of cladded SiOx-Si quantum dots (QDs) forming the gate. Fig. 1(the dashed line shows the anticipated improved behavior in an optimized device), not observed in conventional FETs [2]. That is, the transfer characteristics show three stable
states ("0", "1" and "i"), where the low-current saturation s
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