Temperature Effects on Charge Transfer Mechanisms of nc-ITO Embedded ZrHfO High- k Nonvolatile Memory Devices
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Temperature Effects on Charge Transfer Mechanisms of nc-ITO Embedded ZrHfO High-k Nonvolatile Memory Devices Chia-Han Yang1,2, Yue Kuo1, Chen-Han Lin1 and Way Kuo3 1
Thin Film Nano & Microelectronics Research Laboratory, Texas A&M University, College Station, TX 77843-3122, U.S.A. 2 Department of Industrial and Information Engineering, University of Tennessee, Knoxville, TN 37996, U.S.A. 3 City University of Hong Kong, Hong Kong
ABSTRACT The nanocrystalline ITO embedded Zr-doped HfO2 high-k dielectric thin film has been made into MOS capacitors for nonvolatile memory studies. The devices showed large charge storage densities, large memory windows, and long charge retention times. In this paper, authors investigated the temperature effect on the charge transport and reliability of this kind of device in the range of 25°C to 125°C. The memory window increased with the increase of the temperature. The temperature influenced the trap and detrap of not only the deeply-trapped but also the loosely-trapped charges. The device lost its charge retention capability with the increase of the temperature. The Schottky emission relationship fitted the device in the positive gate voltage region. However, the Frenkel-Poole mechanism was suitable in the negative gate voltage region. INTRODUCTION Silicon dioxide (SiO2) has been used as the gate dielectric of MOS devices for decades. As its thickness is reduced from 3.5 nm to 1.5 nm, the leakage current density increases drastically, e.g., from 10-12 A/cm2 to 10 A/cm2 at a gate bias of 1 V, due to quantum-mechanical tunneling [1]. Currently, there are many researches on replacing SiO2 with a high dielectric constant (high-k) material, such as Si3N4, HfSixOy, HfO2, and ZrO2, to achieve a low leakage current at the same time to improve the device performance and reliability [2]. High-k dielectrics are also critical for nanosize nonvolatile memory (NVM) devices [1]. Recently, the nanocrystals embedded high-k dielectric structure has been proposed to replace the conventional polysilicon floating gate structure for the nonvolatile memory application for advantages of the low operating power and improvement of reliability [3-5]. Due to the low band offset between the high-k film material and silicon, this kind of device requires a low operating power. Therefore, the nanocrystals embedded high-k structure is an attractive structure for the high-density NVM. However, conventional high-k materials such as ZrO2 or HfO2 usually crystallize at a low temperature, e.g., 2.5V. Since the Si/HfSiOx conduction band offset is much smaller than the valence band offset, i.e., 1.5V vs. 3.4V, the Schottky emission mechanism is more pronounced than the F-P conduction mechanism under positive Vg [19]. However, under the negative Vg, the Schottky emission mechanism is overwhelmed by the F-P conduction due to the large valence band offset between Si and HfSiOx.
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(a) (b) Figure 4. J-V curve of the nc-ITO embedded MOS capacitor measured (a) from 0V to +6V and (b) from 0V to -6V
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Figure 5. (a) Fit
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