Test and Diagnosis for Small-Delay Defects
This book introduces new techniques for detecting and diagnosing small-delay defects (SDD) in integrated circuits. Although this sort of timing defect is commonly found in integrated circuits manufactured with nanometer technology, this will be the first
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Mohammad Tehranipoor · Ke Peng Krishnendu Chakrabarty
Test and Diagnosis for Small-Delay Defects
Test and Diagnosis for Small-Delay Defects
Mohammad Tehranipoor • Ke Peng Krishnendu Chakrabarty
Test and Diagnosis for Small-Delay Defects
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Mohammad Tehranipoor ECE Department University of Connecticut 371 Fairfield Way, Unit 2157 06269 Storrs, CT USA [email protected]
Ke Peng Microcontroller Solutions Group Freescale Semiconductor 6501 William Cannon W Dr, OE320 78735, Austin USA [email protected]
Krishnendu Chakrabarty ECE Department Duke University 130 Hudson Hall 27708 Durham, NC USA [email protected]
ISBN 978-1-4419-8296-4 e-ISBN 978-1-4419-8297-1 DOI 10.1007/978-1-4419-8297-1 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2011935996 © Springer Science+Business Media, LLC 2011 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
To my parents MT To my parents, Maojun and Cuicui: Thanks for your encouragement and support KP To my students over the years and to the tradition of excellence that they have established KC
Preface
Electronic devices play a very important part in modern human life. As the demand of the market increases, and the development of manufacturing technologies further advances, more and more transistors are being packed into chips with ever increasing operating frequencies for higher functional density. Nanometer-scale technology poses new challenges for both design and test engineers, since scaling technologies provides us not only with higher integration and enhanced performance in designs, but also with increased manufacturing-related defects. The shrinking of technology has introduced more variation to designs and has made design features more probabilistic. Furthermore, the shrinking of technology, along with the long interconnects required by very large scale designs, has also increased on-chip coupling capacitances. Scaled power supply voltages can be applied to lower power consumption in the circuit. However, reducing the power supply voltage also compromises noise immunity, impacting the signal integrity of the design. On the other hand, the market is always requiring higher test quality and lower failure rates, measured in defects per million (DPM). As a result,
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