Test-Bench Setup for Testing and Calibration of a Newly Developed STS/MUCH-XYTER ASIC for CBM-MUCH Detectors
Compressed Baryonic Matter (CBM) (Senger, J Phys Conf Ser 50(1):357 (2006), [1 ]) is one of the experiments of the upcoming Facility for Antiproton and Ion Research (FAIR) (Senger, J Phys Conf Ser 50(1):357 (2006), [1 ]) in Germany. CBM will take data in
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1 Introduction STS/MUCH-XYTER [2] is a 128-channel dual gain, self-triggered highly configurable hybrid ASIC with about 30,000 settable registers. This ASIC utilizes 180 180 nm CMOS technology in its design and development process. In low-gain setting, this ASIC will be used to readout the CBM [1] MUCH [3] Gas Electron Multiplier (GEM) [4, 5] detectors while high gain setting will be used for STS [6] detectors in the CBM experiment. Outputs of the configurable registers are fed to an associated digital to analog converter (DAC), which controls biasing/trimming voltages of the ASIC at different stages. Without optimizing these bias/trim values, this ASIC cannot be used for any practical application with the detectors. The analog output is fed to a 5-bit flash ADC, where each comparator threshold setting has its own 8-bit trim DAC. The DAC output can drift the threshold voltage of the flash ADC comparator from its nominal value in a limited range. With this flexibility, the ADC in this ASIC can be configured in both linear as well as nonlinear fashion. As there are a huge number of settable registers, hence an automatized test-bench was developed to optimize all the register settings and trim values for the MUCH mode of the ASIC. Figure 1 shows the picture of the STS/MUCH-XYTER board connected with charge injector circuit board at the input connector which can inject charge to all the channels simultaneously. A known charge is injected to the ASIC and the output is readout via the backlink connector as can be seen from the Fig. 1. In this setup, bias/trim parameters are modified automatically in a predefined fashion until an expected response is received at the output for a given input charge. Several software algorithms were applied to the readout data in order to quickly reach the final bias/trim values of an ASIC under test.
2 Architecture of STS/MUCH-XYTER Figure 2 shows the simplified internal block diagram of the STS/MUCH-XYTER ASIC. As can be seen in Fig. 2, detector input is fed through the point DET_IN. Input stage of each channel of this ASIC consists of a charge sensitive pre-amplifier (CSA). CSA has one more input from the internal pulse generator (AMP_CAL), which can feed to 32 channels at the same time. These 32 channels are controlled by a selection switch with predefined sets of 32 channels. Output of the CSA is fed to two shaping circuits, i.e., a fast shaper and a slow shaper via a polarity selection circuit (PSC). With the help of PSC, this ASIC can be used for both positive and negative input charges. The slow shaper has a bigger time constant which can be set in the range of 80–240 ns and is used for energy measurement while the fast shaper has a smaller time constant of 30 ns and is used to determine the timing information of the incoming pulse. Fast shaper has a high gain and its output is fed to a comparator. The comparator output latches the output of a 12-bit counter driven by internal free running clock, where the output corresponds to the timing
Test-Bench Setup
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