Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-U
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Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables Ayan Palchaudhuri1
· Anindya Sundar Dhar1
Received: 14 February 2020 / Accepted: 3 July 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract In this paper, we have achieved run-time dynamic reconfiguration by employing a category of logic cells equipped to realize programmability in Cellular Automata (CA) architectures on Field Programmable Gate Arrays (FPGAs). This is essential for real time VLSI implementations of random number generators, whose functionality requires reconfiguration during runtime, and are called Programmable CA (PCA). The logic cells realizing the PCA are amongst a subset of Look-Up Tables (LUTs) offered by Xilinx FPGAs, known as CFGLUT5. Programmability involves scanning out the contents of the truthtable (TT) originally configuring these LUTs and reconfiguring it with a modified functionality. This feature additionally aids testability which allows to carry out an equality check of the scanned output with a golden copy of the TT contents originally configuring the LUTs during design deployment. Vacant inputs in the LUTs realizing the PCA have been used to establish different scan path arrangements through flip-flops for exercising testability and fault localization further. The entire design flow resulted in a no logic overhead scenario compared to where scan paths did not exist. Any physical FPGA slice coordinate housing a faulty logic element, can be suitably bypassed for future implementations on the same FPGA by applying appropriate placement constraints. Keywords Programmable cellular automata · FPGA · Dynamic reconfigurability · Look-up tables · Fault localization · Scan chain · Primitive instantiation
1 Introduction Field Programmable Gate Array (FPGA) realization of Cellular Automata (CA) has attracted researchers over the years [1–5], owing to the superior acceleration in execution of CA algorithms on hardware, as compared to their equivalent optimized software implementations [6]. Architectural realizations on FPGA when supplemented with an
Responsible Editor: C.-W. Wu Ayan Palchaudhuri
[email protected] Anindya Sundar Dhar [email protected] 1
Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, West Bengal, 721302, India
optimized implementation of testable logic hardware are specially encouraged in the era of reliability challenges [7, 8]. CA finds applications in pseudorandom number generation, cryptography, VLSI testing and computer architectures which support parallel computing [9]. They are readily implementable in VLSI as they can be conducively described as a Finite State Machine (FSM), where the next state (NS) output is governed from the present state (PS) following certain rules [2]. The rules governing the NS of each CA cell are decided by a functionality involving a span of inputs within the nearest neighborhood radius, where the immedia
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