The Behavior of Ion Implanted Silicon During Ultra-High Temperature Annealing
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0912-C04-04
The Behavior of Ion Implanted Silicon During Ultra-High Temperature Annealing Amitabh Jain Silicon Technology Development, Texas Instruments Inc., 13560 North Central Expressway, MS 3737, Dallas, Texas, 75243 ABSTRACT Ultra-high temperature annealing is emerging as a promising technique for annealing ion implanted layers with a view to maximizing electrical activation while minimizing dopant diffusion. In order to ensure successful implementation, several materials-related problems have been under study. Since the time scale of the process is short, diffusion in the amorphous phase may dominate the final profile. In general, the residual disorder after anneal can be higher than with current anneal processes. However, the short time scale of the process curtails the opportunity for movement of dislocations into regions where the electrical behavior of a device would be affected. An additional effect of the limited time scale is the ability of silicon to plastoelastically support the high strain-rates that may arise during the anneal.
INRODUCTION Ultra-high temperature annealing is being applied to the next generation of devices with a view to maximizing electrical activation while minimizing dopant diffusion. The time scale in this process is 1 ms or less. At this short time scale, diffusion in the amorphous phase dominates the final profile as recrystallization persists late into the annealing cycle. In general, the residual disorder after anneal is seen to be higher than with current anneal processes. In order to avoid gross slip it is necessary to understand the plasto-elastic behavior of silicon under conditions of high strain-rate. An understanding of these phenomena can lead to an accurate definition of process requirements. Towards this end, we present the results of experiments that investigate the behavior of ion implanted silicon during ultra-high temperature (uht) cycles. We discuss the mechanical response of the material and the formation of p- and n-type source/drain extensions.
THE PLASTO-ELASTIC RESPONSE OF Si DURING SHORT ANNEALS Spike annealing was introduced at the 130 nm node [1] and has enabled scaling down to the 65 nm node [2-5]. The time spent by the wafer within 50°C of the peak temperature during source/drain anneal is on the order of 1 s. In its most extreme form, this time may be reduced to several tenths of a second. These time durations are long in the context of heat diffusivity in silicon and allow the whole wafer to be at substantially the same temperature throughout the annealing process. Material slip and consequent wafer warpage can be avoided by simply ensuring wafer temperature uniformity through system design and control. This process has been successful in limiting diffusion and supporting device scaling at recent nodes.
slip threshold (°C)
In order to design anneals for continued device scaling, it is necessary to explore further reduction of the time scale. When the time scale for heating is reduced into the millisecond regime, only the region of the wafer co
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