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C4.19.1

The Effect of Oxide Trenches on Defect Formation and Evolution in Ion-Implanted Silicon Nina Burbure and Kevin S. Jones Department of Materials Science and Engineering, University of Florida, Gainesville, FL, 32601, USA

ABSTRACT Pattern induced defects during advanced CMOS processing can lead to lower quality devices with high leakage currents. Within this study, the effects of oxide trenches on implant related defect formation and evolution in silicon patterned wafers is examined. Oxide filled trenches approximately 4000Å deep were patterned into 300 mm silicon wafers. Patterning was followed by ion implantation of Si+ at energies ranging from 10 to 80 keV. Samples were amorphized with doses of 1x1015 atoms/cm2, 5x1015 atoms/cm2, and 1x1016 atoms/cm2. Two independent repeating structures were studied. The first structure is comprised of silicon oxide filled trench lines, 3.7µm wide spaced 12.5µm apart, while the second structure contains silicon squares, 0.6µm on a side, surrounded by a silicon oxide filled trench. Crosssectional and planar view transmission electron microscopy (TEM) samples were used to examine the defect morphology after annealing at temperatures ranging from 700ºC to 950ºC and at times between 1 second and 1 minute. Following complete regrowth, an array of defects was observed to form near the surface at the silicon/silicon oxide interface. These trench edge defects appeared to nucleate at the amorphous-crystalline interface for all energies and doses studied. Upon a spike anneal at 700°C, it was observed that regrowth of the amorphous layer had completed except in the region near the trench edge. Thus, it is believed that this defect results from the pinning of the amorphous-crystalline interface along the trench edge during solid phase epitaxial regrowth (SPER). INTRODUCTION It has been observed that trench structures in ion-implanted silicon wafers can lead to the formation of defects near the trench edge. Such defects may cause device degradation or failure [1-3]. It has been shown that defects along the sides of DRAM trenches lead to increased leakage currents and the need for more frequent refresh cycles [1]. These defects may either form during solid phase epitaxial regrowth (SPER) or possibly after higher temperature processing. One explanation for trench related defects is the migration of point defects to regions of high stress generated by patterned structures [1,4]. Trench edge defects have also been observed to form in high dose arsenic-implanted silicon as a result of amorphous-crystalline interface pinning during SPER [5]. Arsenic implants are also known to introduce additional defects during regrowth, and to this point it is unclear whether the dopant species affects the formation of trench-edge defects [6]. The goal of this study is to investigate by Transmission Electron Microscopy (TEM) the factors influencing the formation of trench edge defects in silicon wafers with non-doping implants.

C4.19.2

EXPERIMENT For this investigation, 300 mm wafers were patterned wit