The gm/ID Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits
How to determine transistor sizes and currents when the supply voltages of analog CMOS circuits do not exceed 1.2V and transistors operate in weak, moderate or strong inversion? The gm/ID methodology offers a solution provided a reference transconductance
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ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES Consulting Editor: Mohammed Ismail. Ohio State University
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The gm/ID Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits The Semi-empirical and Compact Model Approaches By Paul G.A. Jespers Université Catholique de Louvain Louvain-la-Neuve, Belgium
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Prof. Paul G.A. Jespers Université Catholique de Louvain Louvain-la-Neuve Belgium [email protected]
Additional material to this book can be downloaded from http://extra.springer.com. ISBN 978-0-387-47100-6 e-ISBN 978-0-387-47101-3 DOI 10.1007/978-0-387-47101-3 Springer Dordrecht Heidelberg London New York Library of Congress Control Number: 2009940107 c Springer Science+Business Media, LLC 2010 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
to Denise and to my parents Oscar Jespers and Mia Carpentier
Foreword
IC designers appraise currently transistors sizes while having to fulfill simultaneously a large number of objectives like a prescribed gain-bandwidth product, minimal power consumption, minimal area, low-voltage design, dynamic range, non-linear distortion, etc. Making appropriate decisions is not always obvious. How to meet gain-bandwidth specifications while minimizing power consumption of an Op. Amp without area penalty? Should moderate inversion be preferred to strong inversion? Is sizing an art or a mixture of design experience and repeated simulations? Or is it a constrained multivariate optimization problem? Optimization algorithms are attractive without doubt but they require translating not always well-defined concepts into mathematical expressions. The interactions amid semiconductor physics and systems are not always easy to implement. The objective of the book is to devise a methodology enabling to fix currents and transistors widths of CMOS analog circuits so as to meet specifications such as gain-bandwidth while optimizing attributes like low power and small area. A special attention is given to low-voltage circuits. The sizing method takes advantage of the gm =ID ratio and makes use of either ‘semi-empirical’ data or compact models. The ‘semi-empirical’ approach utilizes large look-up tables derived from physical measurements c
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