The Impact of Point Defects on Stress-Induced Dislocation Generation in Silicon
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The Impact of Point Defects on Stress-Induced Dislocation Generation in Silicon
Konstantin V. Loiko, Giri Nallapati, Keith M. Jarreau, Shashank S. Ekbote, Roy A. Hensley, Dale Simpson, Thomas E. Harrington, William R. Frensley,1 and Igor V. Peidous2 Dallas Semiconductor Corporation, 4401 S. Beltwood Parkway, Dallas, TX 75244-3292, U.S.A. 1 The University of Texas at Dallas, 2601 N. Floyd Road, Richardson, TX 75083-0688, U.S.A. 2 The University of the West Indies, Mona, Kingston 7, Jamaica, West Indies ABSTRACT Factors responsible for the onset of dislocation generation in the fields of localized high stresses have been studied in LOCOS-isolated test structures by means of preferential etching, junction leakage analysis, and computer simulation. A strong correlation between densities of stacking faults and dislocations was observed in the experiments. Defect distributions also correlated to leakage currents. 2D simulations of stresses, interstitial injection, and stacking fault growth during field oxidation showed that maximum resolved shear stress in the structures did not exceed the critical level for dislocation generation and that the agglomeration of silicon interstitial atoms did not play a notable role in dislocation nucleation. Dislocation and stacking fault formation was attributed to surface mechanical damage introduced during plasma processing. INTRODUCTION Silicon device structures are highly susceptible to dislocations caused by mechanical stress development during device fabrication [1]. Crystal defects are detrimental for device performance and, therefore, must be avoided. However, mechanisms of dislocation generation in silicon are still not clear in many aspects. In particular, there are no satisfactory quantitative models for the initial stages of stress-induced defect formation. Generation of point defects during oxidation, impurity implantation, and plasma processing of silicon was reported to assist dislocation nucleation [2]. In the present work, the relationship between dislocations and stacking faults, associated with point defects, has been studied. Stress evolution during local oxidation has been analyzed along with point defect redistribution and subsequent stacking fault growth. The results of experiments and calculations are interpreted in terms of factors responsible for the onset of dislocation generation in locally oxidized silicon. EXPERIMENTAL DETAILS 0.35 µm CMOS test devices with LOCOS isolation were fabricated on CZ (100) 150 mm ptype wafers with oxygen concentration 28 - 32 ppm (old ASTM). Some wafers had polysilicon deposited on the backside. A denuded zone was created by high temperature annealing at the beginning of processing. To obtain LOCOS structures with various stress levels, several processes of field oxidation were exercised. Nitride / pad oxide stacks utilized in the experiment were 2000/175, 2000/130, 1200/130, and 1200/90 Å. Plasma etch of nitride films for defining active areas was done using a LAM 4420XL etcher with the standard overetch time optimized for consis
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