Impact of Silicon Wafer Material on Dislocation Generation in Local Oxidation
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defect formation was sensitive to the wafers
supply source. The
evaluation of this interaction regarding the dislocation generation in local oxidation of silicon (LOCOS) is the purpose of the present work. EXPERIMENT CZ (001) silicon wafers from 4 manufacturers were examined. All the wafers met the same specification and were 200 mm p-type boron-doped material with resistivity of about 7.5 Ohm-cm and oxygen concentration of (1.3- 1.4). 1018 cm- 3 (ASTM F1619). The wafers were subjected to advanced local oxidation as part of a LOCOS isolation scheme for sub-half-micron ULSI devices. 450A oxide layer was initially grown on the wafers in the ambient of a dry oxygen at 1000'C and then removed in a buffered HF to achieve identical surface condition for all the wafers. The pad oxide layer of 130A was grown in a dry oxygen ambient at 950'C and LPCVD silicon nitride layer of 2000A was deposited at 760'C at 30A/min. The nitride layer was patterned by means of a conventional lithography and plasma etching. The layout patterns with minimum feature size of 0.4ýim were oriented along the wafer crystallographic directions (110). The wafers were oxidized in wet oxygen at 1100I C to grow 4500A of field oxide. Afterwards, the nitride and oxide films were removed in HF and crystal quality of the wafers was evaluated using Secco preferential etching technique and optical microscopy. On the purpose of the investigation of a depth distribution of defects, cross-sectibns of the wafers were 125 Mat. Res. Soc. Symp. Proc. Vol. 532 01998 Materials Research Society
prepared by cutting along (110) directions and Sirtl etching procedure was used to delineate dislocations on the wafer cleavages. The defect density was evaluated with an optical microscope. RESULTS The specific stress-induced dislocations formed during the LOCOS process were observed on the surface of the wafers as disordered assemblages with high density of dislocations confined by isolated device elements [Fig.l]. The LOCOS structures on the wafers from two of the
Fig. 1. Disordered assemblages of dislocations revealed in device elements on the surface of the LOCOS structure by preferential etching. sources were nearly dislocation-free. The relative number of device elements with dislocations varied from zero to a few percent on the wafers of the other two manufacturers. Extended sets of dislocations were observed on the cross-sections of the structures [Fig.2]. Those sets emanating from the long nitride film edges formed columns of orderly arranged dislocation pileups pushed forward into the bulk of wafers in the {111} planes. They reached a wafer depth of up to a few hundred microns. Based on the analysis of dislocation distribution in the orderly pileups, critical resolved shear stresses 'r,of dislocation movement were determined for the inspected wafers (see Appendix). The values of 'r. were in the range of 1.7 -5.1 MPa and varied considerably from wafer to wafer and from site to site on the same wafer ether.
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Fig.2. The orderly (A) and disorderly (B)
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