The Influence of Stressing at Different Biases on the Electrical and Optical Properties of CdS/CdTe Solar Cells
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The Influence of Stressing at Different Biases on the Electrical and Optical Properties of CdS/CdTe Solar Cells S. W. Townsend, T. R. Ohno, V. Kaydanov, A. S. Gilmore, J. D. Beach, and R. T. Collins Colorado School of Mines, Dept of Physics 1523 Illinois St. Golden, CO 80401, U.S.A. ABSTRACT Cadmium Sulfide/Cadmium Telluride (CdS/CdTe) devices are subject to stress under various biases. Striking differences are observed with the Current-Voltage, and CapacitanceVoltage measurements for cells degraded at 100°C in dark under forward (FB), open circuit (OC), and reverse (RB) biases. RB stress provides the greatest degradation, and the apparent doping density profile shows anomalous behavior at the zero bias depletion width. Thin films of CdS, both doped and undoped, with Cu are characterized with photoluminescence (PL). The PL spectra from the CdS films are correlated with the CdS spectra from stressed devices, revealing that Cu signatures in the CdS layer of stressed devices are a function of stress biasing. Device modeling using AMPS-1D produces IV curves similar to that in RB degraded devices, by only varying the trap level concentration in the CdS layer. INTRODUCTION In an attempt to reveal mechanisms for device failure, CdS(n-type)/CdTe(p-type) solar cells are routinely subject to degradation experiments [1]. The influence of Cu in device degradation is of particular interest. In an effort to reduce the Schottky diode effect, Cu is added to the CdTe device near the back contact metallurgical interface. This creates a p+ region resulting in near-ohmic behavior [2-4]. Unfortunately, Cu can migrate from the back contact, and its presence is observed in the CdS layer and at the CdS/CdTe interface [4-6] in unstressed devices. Since a decrease in Cu concentration at the back contact interface is detrimental to the contact quality, the focus of efficiency loss in stressed devices is often placed solely on the back contact. As such, stress induced effects residing in the CdS layer are largely unexplored. For CdTe devices, the electrical activity of diffused Cu into the CdS layer is unknown. Strong evidence suggests that Cu diffuses through CdTe into CdS via grain boundaries [6]. Once present in the CdS, Cu is then available for diffusion into the bulk material of this layer. It has been shown that Cu can dope CdS p-type [7]. Therefore, its presence in the CdS layer may contribute to device degradation through compensation. Non-destructive techniques that can monitor layer specific degradation are thus needed. PL is a tool that can indicate Cu migration with bias stressing, and help reveal the electrical nature of diffused Cu within the CdS. EXPERIMENTAL DETAILS Back contacts are fabricated at the Colorado School of Mines (CSM) on supplied material, resulting in a complete device of glass/TCO/CdS/CdTe/back-contact. The glass is the substrate, the TCO (or transparent conducting oxide) provides the front contact, and the H5.11.1
CdS/CdTe is referred to as the main junction. The near-ohmic contact is obtained in two steps: 1
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