The origin of gate bias stress instability and hysteresis in monolayer WS 2 transistors
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State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China 2 School of Optoelectronic Science and Engineering, University of Electronic Science and Technology of China, Chengdu 610054, China 3 Department of Materials Science and Engineering, City University of Hong Kong, Kowloon 999077, Hong Kong, China 4 State Key Laboratory of Terahertz and Millimeter Waves, City University of Hong Kong, Kowloon 999077, Hong Kong, China 5 Key Laboratory of Advanced Materials Processing & Mold of Ministry of Education, Zhengzhou University, Zhengzhou 450002, China © Tsinghua University Press and Springer-Verlag GmbH Germany, part of Springer Nature 2020 Received: 23 June 2020 / Revised: 16 July 2020 / Accepted: 20 July 2020
ABSTRACT Due to the ultra-thin nature and moderate carrier mobility, semiconducting two-dimensional (2D) materials have attracted extensive attention for next-generation electronics. However, the gate bias stress instability and hysteresis are always observed in these 2D materials-based transistors that significantly degrade their reliability for practical applications. Herein, the origin of gate bias stress instability and hysteresis for chemical vapor deposited monolayer WS2 transistors are investigated carefully. The transistor performance is found to be strongly affected by the gate bias stress time, sweeping rate and range, and temperature. Based on the systematical study and complementary analysis, charge trapping is determined to be the major contribution for these observed phenomena. Importantly, due to these charge trapping effects, the channel current is observed to decrease with time; hence, a rate equation, considering the charge trapping and time decay effect of current, is proposed and developed to model the phenomena with excellent consistency with experimental data. All these results do not only indicate the validity of the charge trapping model, but also confirm the hysteresis being indeed caused by charge trapping. Evidently, this simple model provides a sufficient explanation for the charge trapping induced gate bias stress instability and hysteresis in monolayer WS2 transistors, which can be also applicable to other kinds of transistors.
KEYWORDS charge trapping, gate bias stress instability, hysteresis, WS2, transistor
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Introduction
In the past decades, silicon-based transistors have been the major workhorse for countless technological applications, such as integrated circuits, displays and many others. The characteristic length of silicon devices has then followed Moore’s Law to scale below 5 nm in the current technology [1]; however, the continuous device down-scaling is extraordinarily challenging due to various issues, which include short channel effect, drain induced barrier lowering, etc. [2]. One proved solution is to utilize device channel materials with the atomic thickness in order to eliminate the adverse effect of device scaling [3]. In this case, since the surface states arising from
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