Time-Dependent Bias Stress-Induced Instability of SiC MOS Devices
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0911-B13-05
Time-Dependent Bias Stress-Induced Instability of SiC MOS Devices Aivars Lelis1, Daniel Habersat1, Fatimat Olaniran1, Brian Simons1, James McGarrity2, F. Barry McLean2, and Neil Goldsman3 1 U.S. Army Research Laboratory, Adelphi, MD, 20783 2 Berkeley Research Associates, Springfield, VA, 22150 3 Electrical and Computer Engineering, University of Maryland, College Park, MD, 20742
ABSTRACT We have observed a gate-bias stress induced instability in both the threshold voltage of SiC MOSFETs and the flatband voltage of SiC MOS capacitors. The magnitude of this bias stress-induced instability generally increases linearly with log time, with no saturation of the effect observed, even out to 100,000 seconds. The magnitude also increases with increasing gate field. A positive gate-bias stress causes a positive shift and a negative gate-bias stress causes a negative shift, consistent with electron tunneling into or out of oxide traps near the SiC / SiO2 interface as opposed to mobile ions drifting across the gate oxide. The effect is repeatable. INTRODUCTION Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) are very attractive devices, allowing voltage controlled transistor operation at high temperature, high frequency, and high power levels with limited cooling requirements. However, charge trapping at and near the SiC-silicon dioxide (SiO2) gate insulator interface can lead to degradation in device performance and reliability. Effects include decreased channel mobility due to Coulombic scattering, reduced effective mobility due to reduction in the free carriers in the channel [1], shift of the threshold voltage (VT), and instability of the threshold voltage [2]. According to the Deal committee formulation for silicon [3], this charge in general can be due to interface traps (NIT), oxide traps (NOT), fixed charge (NF), and mobile ions (NM). Interface traps have long been a concern, and a great deal of effort has been exerted in finding processing steps that reduce these densities [4]. Mobile ions have not been an issue, but fixed charge and oxide trapped charge have. A balancing of this charge with interface traps in n-channel MOSFETs have led to reasonable threshold voltages. However, by reducing NIT, this can lead to a shift in the threshold voltage to negative values. A change in the balance of the different types of trapped charge can also change the percentage of free carriers in the channel. Finally, oxide traps are probably the cause of instabilities observed in the threshold voltage following gate-bias stressing. EXPERIMENT 4H SiC MOSFETs with both thermally grown and deposited gate oxides were gate-bias stressed as a function of both time and electric field. Similarly, MOS capacitors were gate-bias stressed as well. The n-channel MOSFETs in this study were both bias-stressed and measured
using an Agilent 4155 Semiconductor Parameter Analyzer. Initially, the gate bias was swept up in voltage while applying a small drain bias in order to analyze the drain current-gate v
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