The Role of Process Choices in Reliability Fail Modes
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INTRODUCTION Projections on density, performance and cost attributes of a new technology generation are relatively easy to accomplish. However, defining the reliability attributes is more problematic, particularly if the technology contains many new process elements or tools. The choices made by a development team for processes, tools, process sequences and product-layout rules often determine the process defect reliability fail modes of a technology. These process defects define the reliability level of products rather than classic reliability fail mechanisms such as electromigration, stress migration and corrosion. As such, development teams and their reliability counterparts need to focus on potential sources of process-defect reliability fail modes and their control. A discussion of process and tool-related defects is particularly relevant at this time. The integrated circuit (IC) industry has used the same basic materials and processes for the past quarter-century: aluminum or aluminum-based alloys for wiring and silicon dioxide as the primary insulator. The mainstream patterning technique has been subtractive etch of both metals and vias; etch processes have changed from wet chemical to dry RIE technology but both techniques are subtractive. Given the experience level with this relatively stable technology base, most process-defect reliability fail modes are known. Semiconductor industry roadmaps now reflect migration to copper-based wiring and low dielectric constant insulators within the next few technology generations. Patterning techniques for metals may also change from subtractive to additive. The process-defect reliability fail modes for this new interconnect technology are mostly unknown. Understanding and controlling these reliability fail modes could be the factor that gates adoption of copper wiring and low dielectric constant insulators into mainstream IC manufacturing.
TOOL-SPECIFIC RELIABILITY FAILS Specific tools are often the source of process defects which also cause reliability fails. For example, the sputtered-quartz deposition tooling [1] used from 1970 - 1985 in some of our manufacturing fabricators was the source for quartz flake related reliability fails. The sputtered quartz films were used for passivation and as inter-level metal insulators. Figure 1 depicts the pareto chart of 1972 field returns for a single level metal memory product with sputtered quartz passivation. As can be seen, 10% of the reliability returns were attributed to sputtered quartz. Characterization of the reliability fails showed etched holes caused by quartz flakes which extended through the resist via mask and served as an ingress point for the etchant. Damage to the via 37 Mat. Res. Soc. Symp. Proc. Vol. 391 0 1995 Materials Research Society
40% 37.5%
No
Gate Defects
Defects Found
12.5%
10%
Other
Quartz
Holes Figure 1. 1972 field return reliability fails: FET memory product.
photo mask by the quartz flakes during the contact printing expose process was another identified mechanism which caused etche
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