The Simple Art of SoC Design Closing the Gap between RTL and ESL
This book tackles head-on the challenges of digital design in the era of billion-transistor SoCs. It discusses fundamental design concepts in design and coding required to produce robust, functionally correct designs. It also provides specific techniques
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Michael Keating
The Simple Art of SoC Design Closing the Gap between RTL and ESL
Michael Keating Synopsys 1925 Cowper St. Palo Alto, CA 94301 USA [email protected]
ISBN 978-1-4419-8585-9 e-ISBN 978-1-4419-8586-6 DOI 10.1007/978-1-4419-8586-6 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2011924222 © Synopsys, Inc. 2011 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
Disclaimer
Because of the possibility of human or mechanical error, neither the author, Synopsys, Inc., nor any of its affiliates, including but not limited to Springer Science+Business Media, LLC, guarantees the accuracy, adequacy or completeness of any information contained herein and are not responsible for any errors or omissions, or for the results obtained from the use of such information. THERE ARE NO EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE relating to this book. In no event shall the author, Synopsys, Inc., or its affiliates be liable for any indirect, special or consequential damages in connection with the information provided herein.
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Foreword
A new graduate may think: “SoC design is exciting; I want to design chips for SmartPhones!” But, experienced RTL designers know that the reality of SoC design is more than exciting. It takes blood, sweat and tears to wrestle up to 20 Million lines of Verilog code into a production-ready product. Chip companies apply manpower, the latest tools and very sophisticated methodologies to find and fix the bugs in an SoC before it goes to silicon – bugs that can run into the thousands. Hardware designers take pride in the fact that, out of necessity, they routinely create higher quality code than software developers. Unlike software that is often fixed after the product is shipped, the hardware must be essentially bug-free before tape-out. As design size and complexity has grown dramatically, it has become much harder for hardware design teams to live up to this promise. The result is often called the “verification crisis.” The design community, along with the EDA industry, has responded to this crisis by making significant improvements in verification technology and meth
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