Theoretical and Experimental Understanding of Charge-Injection GeTe/Sb 2 Te 3 Superlattice Phase Change Memory
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Theoretical and Experimental Understanding of Charge-Injection GeTe/Sb2Te3 Superlattice Phase Change Memory Norikatsu Takaura Low-power Electronics Association & Project, Onogawa, Tsukuba, Ibaraki, 305-8569, Japan ABSTRACT A charge-injection GeTe/Sb2Te3 superlattice phase change memory (PCM or PRAM) has been developed as a candidate for a non-volatile memory that replaces NAND flash memory. It differs from PRAM with the conventional material of GeSbTe, and is therefore named “TRAM (topological switching random access memory)”. First principle calculations showed a resistance change in the GeTe/Sb2Te3 superlattice was enhanced by charge injection. The fabrication and analyses of a one-resistor TEG revealed that the superlattice structure was maintained after 1M endurance, which proved the occurrence of non-melting resistance change in TRAM. The reset current of TRAM was found to be less than 1/5 of that of conventional PRAM. Furthermore, TRAM enables a set -speed of 10 ns and reset -operation by DC-sweep to be achieved, which experimentally proved the atomic movement in TRAM can be enhanced by charge injection. INTRODUCTION “Big Data” are huge amounts of data that are generated in conjunction with the development of IT and IoT (Internet of Things) technologies. The need for storing and utilizing “Big Data” is growing. The bit capacity of desk storage in data centers in the year 2020 will become 10 times larger than that in 2014. Simultaneously, the speed of data storage in data centers in 2020 will become faster than that in 2014 by an order of one magnitude [1]. This will particularly hold at the highest level of the storage –system hierarchy, called tier -zero. The amount of data stored in tier -zero is only about 5% of the total data. However, the frequency in use of the tier -zero storage reaches about 80% of that of the total system. Therefore, achieving high-speed processing in tier -zero will be an issue to be solved in next -generation data centers. The demand for high -speed processing with low -power consumption has been satisfied by the adoption of solid state drives (SSDs), and the random performances of SSDs are much better than those of hard disk drives (HDDs). The power consumed by SSDs is less than that consumed by HDDs since semiconductor memory chips do not require mechanical motions that are indispensable with HDDs [2]. NAND flash memories are widely used in SSDs as non-volatile memories (NVMs). While NAND flash memory chips have satisfied the requirements for the current –generation SSDs, this may not be the case in the near future. Complicated operations such as block erase and wear leveling will prevent improvements in speed and power consumption in NAND flash memories. The next generation SSDs will require NVMs with properties that NAND flash memories do not have. Resistive -switching memories have been investigated as candidates for NVMs to replace NAND flash memories. While NAND flash memories store bit -data by storing electrons, resistive -switching NVMs store them by changing resistance. T
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