Understanding Phase Change Memory Reliability and Scaling by Physical Models of the Amorphous Chalcogenide Phase
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Understanding phase change memory reliability and scaling by physical models of the amorphous chalcogenide phase Daniele Ielmini Dipartimento di Elettronica e Informazione and IU.NET, Politecnico di Milano, Piazza L. da Vinci, 32 – 20133 Milano, Italy. Email: [email protected] ABSTRACT Phase change memory (PCM) devices are based on the electrically-induced change of phase within an active chalcogenide material. PCM features large resistance window, fast threshold/phase switching and high endurance, thus motivating a broad interest as potential Flash replacement and/or nonvolatile storage class memory. Despite the relatively mature progress of research and technology, there is still a wide debate about the ultimate scaling perspective for PCMs. Structural relaxation, crystallization and noise affecting the amorphous chalcogenide phase need to be addressed by accurate physical models for a realistic scaling projection. This work discusses the scaling of PCM devices in terms of the conduction mechanisms and structural stability of the amorphous chalcogenide phase. Resistance window narrowing, current fluctuations, resistance drift and crystallization in the amorphous phase will be explained by a unified model for thermal excitation of the structure by many-phonon phenomena. The downscaling of the reset current, needed to reduce the cell area in memory arrays, and thermal disturb between adjacent cells during reset will be finally addressed to assess the scaling capability of high-density PCM crossbar architectures. INTRODUCTION PCM relies on the reversible phase change in an active chalcogenide material, typically Ge2Sb2Te5 (GST). The two logic states in the memory are encoded as different phases in the active material, namely the amorphous and crystalline phases for the reset and set states, respectively. Thanks to the large resistivity difference between the amorphous and crystalline phases, PCM features a large resistance window of about 2 to 3 orders of magnitudes [1]. The high crystallization speed allows for program/erase times largely below 1 µs, thus compatible with NOR applications and storage class memories combining fast set/reset, non-volatility and high cell density [2]. PCM technology development has recently made tremendous progress, reaching the target of a 45nm–generation node [3] and providing demonstrations of crossbar architectures with the potential of 3D memories with extremely high density [4,5]. Figure 1 shows a TEM cross-section of an active PCM region in the high-resistance (reset) state, evidencing the programmed amorphous volume within the crystalline GST film and the bottom electrode [6]. The amorphous cap is formed during the reset operation, when an electric pulse yields Joule heating and consequent melting in a GST region above the bottom electrode. The sudden drop of temperature at the end of the pulse results in a swift quenching of the molten GST region, which then remains in a disordered, glassy phase. The set operation is then used to recover the polycrystalline ph
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