Thermal stress characteristics of two-level Al(Cu) interconnect structure
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Thermal stress characteristics of single-level and two-level Al(Cu) interconnects passivated with tetraethyl orthosilicate oxide were measured using x-ray diffraction. Thermal stresses of the second-level metal lines were deduced from the experimental data based on an analysis of the x-ray absorption in a two-level interconnect structure. The confinement effect from the substrate on the stress characteristics of metal lines at different interconnect levels was investigated. Thermal stress behavior of the second-level lines indicated that the confinement effect from the Si substrate is reduced compared to the single-level lines, resulting in reduced levels of hydrostatic and shear stresses.
I. INTRODUCTION
Al and Al(Cu) alloys have been used as interconnect metallization for more than three decades, and the stress behaviors have been studied by several research groups both experimentally and theoretically.1–15 The fabrication of interconnect structures usually requires several thermal cycles from room temperature to about 400 °C, and the build up of stresses due to thermal mismatches between different materials is a major reliability concern. Previous studies on the thermal stresses of Al(Cu) lines passivated with oxide dielectric indicate that the lines are subject to a triaxial tensile stress state upon cooling from high temperatures. The thermomechanical confinement due to the substrate and the interlevel dielectric layer plays an important role in controlling the stress level of the metal lines. The magnitude of the stress was found to increase with decreasing line widths, and the stress level can reach as high as 850 MPa for lines with deep submicron line widths.9 Since large hydrostatic tensile stress acts as a driving force to induce void formation, this is a major reliability concern as the line dimension scales continuously to improve the density and performance of integrated circuits. Although actual interconnect structures typically consist of 7–9 levels of metal layers in the case of microprocessors and 3–4 levels in case of memory devices, simplified structures of single level have been used almost exclusively for the study of stress characteristics a)
Present address: Advanced Micro Devices, Inc., One AMD Place, P.O. Box 3453, M/S 143, Sunnyvale, California 940883453. e-mail: [email protected]
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J. Mater. Res., Vol. 18, No. 4, Apr 2003 Downloaded: 17 Mar 2015
in interconnects. The metal lines of the first-level interconnects have the smallest dimension and are located closest to the substrate. This causes the highest stress level in the metal lines, making them most susceptible to stress-induced void formation. The line dimension of the second-level interconnects is usually comparable to that of the first-level lines, but the lines separate further away from the substrate. This raises an interesting question regarding the thermal stress behavior of the metal lines on the second level. So far, the information on the stress behavior of multilevel interconnects
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