Three Dimensional Interconnect Stress Modeling for Back End Process
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Three Dimensional Interconnect Stress Modeling for Back End Process Xiaopeng Xu and Victor Moroz TCAD R&D, Synopsys, Inc. 700 E. Middlefield Rd, Mountain View, CA 94043, USA ABSTRACT A process oriented approach is demonstrated for modeling the stress evolution during the entire back end process flow. No ad hoc assumptions regarding stress states are made for layer deposition and etching. Intrinsic stresses from material formation, thermal mismatch stresses from temperature ramps, stress relaxation due to viscous deformation, and stress profile redistribution upon deposition and etching are all considered at each process. Parametric studies are carried out to examine the effects of viscous flow, material selection and layout variations. It is found that the viscous flow of the passivation and dielectric materials have large impact on stress evolution. A TCAD assisted design approach is suggested for lowering stress levels of critical stress components. The implications of the stress modeling results on reliability issues like stress-triggered void formation are discussed. INTRODUCTION In modern integrated circuits, interconnects consist of multilevel metal lines that are embedded within several layers of different dielectric materials above the silicon transistors. The materials in interconnects have very different mechanical properties. These differences can lead to large thermal mismatch stresses during the fabrication process. The residual stresses in interconnects are known to cause yield and reliability issues. Predicting stress and deformation fields in interconnects for reliability assessments and yield improvements has been a major effort in the semiconductor industry and in the research community [1,2]. Historically, interconnect stresses are modeled with various assumptions. For example, 2D plane strain or 2D axisymmetric simplifications are made for a 3D structure; viscous relaxation in low-k dielectric insulators are ignored; and ad hoc numerical treatments are introduced to activate and deactivate elements in the mesh instead of layer deposition and etching [3,4]. Stress simulations with such assumptions become increasingly inadequate to predict stress distributions inside interconnects that are fabricated with complex process flows. In this study we use our three-dimensional process simulator to simulate the stress evolution during the entire interconnect fabrication process which includes material deposition and etching steps at room temperature and elevated temperatures, and temperature ramps in between. Stresses are generated during the temperature ramps due to thermal expansion mismatches, relaxed in the meantime because of viscous deformations, and redistributed during deposition and etching due to the rebalance of forces. The thermal stress generation, relaxation and redistribution are considered at each process step by solving stress equations for realistic evolving geometry during deposition and etching steps. MODELS A typical interconnect structure consists of materials with strikingly
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