Thin Film Characterization on Cu/SnAg Solder Interface for 3D Packaging Technologies
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MRS Advances © 2020 Materials Research Society DOI: 10.1557/adv.2020.309
Thin Film Characterization on Cu/SnAg Solder Interface for 3D Packaging Technologies Kimberly Beers1,2, Andrew E. Hollowell2, G. Bahar Basim1 1
University of Florida, Materials Science and Engineering Department, Gainesville, FL 32611
2
Sandia National Labs, Microsystems Integration, Albuquerque, NM 87123
ABSTRACT
Copper is a commonly used interconnect metal in microelectronic interconnects due to its exceptional electrical and thermal properties. Particularly in applications of the 2.5 and 3D integration, Cu is utilized in through-silicon-vias (TSVs) and flip chip interconnects between microelectronic chips for providing miniaturization, lower power and higher performance than current 2D packaging approaches. SnAg capped Cu pillars are a common high-density interconnect technology for flip chip bonding. For these interconnects, specific properties of the Cu surface, such as roughness and cleanliness, are an important factor in the process to ensure quality solder bumps. During electroplating, tight processing parameters must be met so that defects are avoided, and high bump uniformity is achieved. An understanding of the interactions at the solder and Cu pillar interface is needed, based on the electroplating parameters, to determine the best method for populating solder on the wafer surface. In this study, surface treatment techniques such as oxygen plasma cleaning were performed on the Cu surfaces and the SnAg plating chemistry for depositing the solder were evaluated through hull cell testing to qualitatively determine the range of current densities to investigate. It was observed that current density while plating played a large role in solder bump deposition morphology. At the higher current densities greater than 60 mA/cm2, bump height nonuniformity and dendritic growth are observed and at lower current densities, less than or equal to 60 mA/cm2, uniform, continuous bump height occurred. 1
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INTRODUCTION Mutli-chip stacking and heterogeneous integration (HI) has the ability to improve performance and reduce size, weight, and power (SWaP) for microelectronics packaging architectures as compared to more traditional 2-D packaging approaches. In these 2.5 and 3-dimentional (3D) integration schemes, copper metallization is utilized for through-silicon-vias (TSVs) and flip chip bonding [1]. Flip chip bonding techniques such as IBM’s Controlled collapse chip connection (C4) are used in the microelectronics packaging industry to connect chips by means of electrically conductive solder bumps between the two chip surfaces allowing miniaturization and better performance [2]. C4 approaches have limits in interconnect density because as the pitch between interconnects scales to lower than ~100 µm, the bond line
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