Interface Adhesion and Reliability of Microsystem Packaging
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Interface Adhesion and Reliability of Microsystem Packaging Marvin I. Francis, Kellen Wadach, Satyajit Walwadkar and Junghyun Cho Dept. of Mechanical and Materials Engineering, State University of New York, Binghamton, NY 13902-6000 ABSTRACT Flip-chip technology is becoming one of the most promising packaging techniques for high performance packages. Solder balls are used as the connection technique in the flip-chip method and the connections are reinforced by filling in the spacing between the chip and substrate with underfill. The function of the underfill is to reduce the stresses in the solder joints caused by a coefficient of thermal expansion (CTE) mismatch. The presence of polymeric underfill material will, however, make the flip-chip packaging system susceptible to interfacial failure. Thus, the purpose of this study is to examine the interfacial delamination between the dissimilar materials in order to increase the reliability of the flip-chip interconnection method, and to understand the effect of underfill curing conditions on the interface adhesion. In particular, we use a linear elastic fracture mechanics (LEFM) approach to assess interfacial toughness. For this purpose, four-point bending testing is performed to determine a critical strain energy release rate, Gc. In addition, nano-indentation testing equipped with atomic force microscope (AFM) is employed to determine structure and properties of the underfill layer. INTRODUCTION Traditional packaging techniques are being replaced by the flip-chip/solder ball array packaging technique due to its increased input/output count, which increases performance [1]. The flip-chip interconnection system is a multilayer structure that is composed of a silicon die, solder balls, substrate, and underfill material. As a result, several interfaces are formed, including the silicon die/passivation, passivation/underfill, underfill/solder joint, underfill/solder mask, and solder mask/circuit board. The mechanical integrity of these different interfaces is, therefore, important in the reliability of the flip-chip package [2-5]. The interfaces that have proven to be a major source of delamination caused by a coefficient of thermal expansion (CTE) mismatch are the underfill/SiO2 layer and the underfill/SiNx passivation layer [4,5]. Underfill is composed of silica-filled epoxy resin, and fills in the spacing between the IC and the substrate, thereby minimizing the stresses on the solder joints. Delamination at these interfaces is caused by low fracture energy, which can lead to rapid fatigue crack growth into the solder joints. Given that, we employ a reliable and repeatable LEFM based testing procedure that can be applied to examine the interfacial properties, particularly in flip-chip packages [6-10]. One objective of this research is to explore fundamental understanding on mechanical performance of the interfaces found in flip chip packages. This will be of greater importance when the packaging system becomes smaller as is the case for MEMS and MOEMS packaging.
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