Three-Dimensional Integration of Silicon Chips for Automotive Applications
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0970-Y03-01
Three-Dimensional Integration of Silicon Chips for Automotive Applications Werner Weber AIM TI MU FP, Infineon Technologies, Am Campeon 1-12, Munich, 81726, Germany
ABSTRACT Currently, three-dimensional (3D) integration of semiconductor chips is in the phase of introduction in high-volume products. While memory and communication are the leading fields of application, automotive use requires specific non-standard solutions. Some of these solutions are still being researched or are in development, whereas others are already in production. This paper elaborates on the different opportunities and constraints of automotive applications, presents different technological options, and discusses specific solutions. INTRODUCTION In the early 1990s, groups at NEC [1-2] and Tohoku University [3-4] first introduced the concept of 3D stacking of fully-processed chips as an alternative to successive processing of various CMOS layers on top of one another. In 1983, this idea was taken up by a collaboration of Siemens and FhG in a research project on 3D integration. The Inter-Chip Via (ICV) process was developed [5-6] and thermal and speed performance properties were first discussed [7-12]. Since then, many groups have joined the 3D stacking community and fostered developments of various technological variants of stacking, and discussed their business values. Recently, those activities intensified with interest focusing on stacks for memory and communication. The automotive field has its own opportunities and constraints; we discuss that field in this paper. First, we provide an overview of important concepts and constraints of different areas of application, and discuss different technological options. Then we present typical automotive parameter sets and various automotive applications, and discuss the best-suited solutions. BACKGROUND ON 3D INTEGRATION FOR AUTOMOTIVE APPLICATIONS Opportunities and constraints for 3D integration In 25 years of research on 3D integration of silicon chips, two directions of activity have evolved. One is the performance-optimized integration of chips. Each chip within the 3D stack is produced in the same state-of-the-art logic process. This concept aims for performance improvements on the chip system level. The number of interconnects is high, and consequently the testability of the single die is difficult if not impossible. Testing can only be performed after stacking; the disadvantage is that the whole stack will have to be discarded if only one die is bad. This reduces the overall yield. However, there is a good chance of improving the performance of computing by replacing long horizontal contacts with short vertical contacts. As a consequence, the number of repeaters can be reduced, further reducing the signal propagation time.
The other direction is form-factor-optimized integration of chips from different or equal processes into one stack. Communication between the chips is conducted at the interface between different logic blocks. As a consequence, the number of interchip conne
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