Three-Dimensional Integration Technology Based on Self-Assembled Chip-to-Wafer Stacking
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1112-E02-07
Three-Dimensional Integration Technology Based on Self-Assembled Chip-to-Wafer Stacking
Takafumi Fukushima, Tetsu Tanaka, and Mitsumasa Koyanagi Department of Bioengineering and Robotics, Tohoku University, 6-6-01 Aza-Aoba, Aramaki, Aoba-ku, Sendai, 980-8579, Japan
ABSTRACT We have demonstrated that a number of known good dies (KGDs) can be precisely aligned in batch and stacked on LSI wafers by our chip-to-wafer three-dimensional (3D) integration technology using an innovative self-assembly technique. Compared with conventional robotic pick-and-place chip assembly, the fluidic self-assembly can provide highthroughput chip alignment and bonding, and the resulting self-assembled chips have high alignment accuracy of approximately 0.3 µm on average. Immediately after chip release, the chips are aligned onto the predetermined hydrophilic bonding areas in a short time within 0.1 sec by the surface tension of aqueous liquid used in our self-assembly. By using the self-assembly, a number of KGDs with different chip sizes, different materials and different devices can be stacked in high yield to give highly integrated 3D chips we call the 3D Super Chip.
INTRODUCTION 3D integration has attracted much attention since vertically stacked chips with large numbers of Through-Silicon Vias (TSVs) can decrease chip size and shorten the length of long wirings interconnecting between functional blocks, and consequently, dramatically improve LSI performance [1]. In the recent 10 years, we have developed various types of TSVs with polycrystalline silicon (Poly-Si) [2], Poly-Si/Tungsten [3], and Tungsten [4] as conductive materials and fabricated prototype 3D LSI chips such as an image sensor chip [5], a shared memory [6], an artificial retina chip [7], and a microprocessor chip [8] by using a wafer-to-wafer bonding technique. The first 3D integration based on wafer–to-wafer stacking is proposed in 1989 [9], where LSI wafers are temporarily bonded onto quarts glasses, and then, thinned from the backside, followed by the wafer alignment and bonding. The wafer-to-wafer 3D integration is a promising candidate for high-throughput stacking of memories such as Dynamic Random Access Memory (DRAM). However, a major problem in the wafer-to-wafer 3D integration is that production yield exponentially decreases with the increase in the number of stacked wafers because defective dies can not be removed from completed LSI wafers to be stacked. On the other hand, chip-to-wafer 3D integration can provide high production yield due to the use of Known Good Dies (KGDs) [10], [11]. Figure 1 illustrates traditional robotic pick-and-place chip assembly processes. The serious disadvantage is that it takes much time to precisely align and
tightly bond many KGDs onto an LSI wafer by the pick-and-place assembly used in the conventional chip-to-wafer 3D integration. In 2005, we have proposed 3D integration technology based on a new self-assembled chip-to-wafer bonding technique to solve the big throughput problem in the chip-to-wafer 3D integrat
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