High Density Bond Interconnect (DBI) Technology for Three Dimensional Integrated Circuit Applications
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0970-Y01-04
High Density Bond Interconnect (DBI) Technology for Three Dimensional Integrated Circuit Applications Paul Enquist Ziptronix, Inc., 800 Perimeter Park, Suite B, Morrisville, NC, 27560
ABSTRACT A novel direct wafer bonding technology capable of forming a very high density of electrical interconnections across the bond interface integral to the bond process is described. Results presented include an 8 um interconnection pitch, die-to-wafer and wafer-to-wafer bonding formats, temperature cycling reliability x10 greater than the JEDEC requirement, connection yield ~ 99.999, > 50% part yield on parts with ~ 450,000 connections, and < 0.1 Ohm connection resistance at 1pA without requiring a voltage surge to induce current. INTRODUCTION Conventional two dimensional integrated circuit (2D IC) technology is approaching scaling limits as transistor dimensions continue to shrink and the number of interconnect layers continue to grow [1]. Three dimensional integrated circuits (3D ICs) fabricated from stacked or bonded 2D ICs have the potential to alleviate these scaling limits and allow continued increase in performance by reducing signal delays with vertical interconnects and reductions in cost by partitioning integrated circuit design and fabrication into separately optimized process nodes. 3D IC fabrication has requirements above that of conventional 2D fabrication due to the 3D stacking and vertical interconnection. Realizing the full potential of 3D IC technology will require the identification and adoption of a scaleable approach to 3D IC fabrication to extend performance and reduce cost as much as possible. Key additional 3D IC fabrication requirements are a silicon via etch and fill through the silicon transistor layer in one of the stacked 2D ICs that provides for a 3D vertical electrical interconnection between two stacked 3D ICs, the pitch of vertical interconnects between two stacked 3D ICs, and cost. Silicon Via Etch and Fill Approaches There are two primary options in the approach to implementing the 3D IC silicon via etch and fill process. The first option is etching and filling the silicon vias either before or after the bonding of the two 2D ICs. The second option is etching and filling the silicon vias either through the back-end-of-line (BEOL) interconnect stack and the front-end-of-line (FEOL) silicon transistor layer or only through the (FEOL) silicon transistor layer. Different combinations of these two options allow the predominant silicon via etch and fill approaches to be categorized into the three different categories discussed below.
After Bonding and Through BEOL and FEOL In this approach, the two 2D ICs are first bonded and then the silicon via is etched and filled. This approach can be implemented with the two 2D ICs either bonded BEOL-to-BEOL (face-to-face) or BEOL-to-FEOL, (face-to-back). The BEOL-FEOL implementation has the advantage of better isolation between the bonded 2D ICs, but may have the disadvantages of 1) a longer vertical interconnection between the two 2D ICs and 2)
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