Effect of SiC Power DMOSFET Threshold-Voltage Instability
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Effect of SiC Power DMOSFET Threshold-Voltage Instability A.J. Lelis1, D. Habersat1, R. Green1, A. Ogunniyi1, M. Gurfinkel2, J. Suehle2, and N. Goldsman3 1 U.S. Army Research Laboratory, 2800 Powder Mill Rd, Adelphi, MD, 20783 2 NIST, Gaithersburg, MD, 20899 3 University of Maryland, College Park, MD, 20742 ABSTRACT We have performed bias-stress induced threshold-voltage instability measurements on fully processed 4-H SiC power DMOSFETs as a function of bias-stress time, field, and temperature and have observed similar instabilities to those previously reported for lateral SiC MOSFET test structures. This effect is likely due to electrons tunneling into and out of nearinterfacial oxide traps that extend spatially into the gate oxide. As long as the threshold voltage is set high enough to preclude the onset of subthreshold drain leakage current in the blocking state, then the primary effect of this instability is to increase the on-state resistance. For wellbehaved power DMOSFETs, this would increase the power loss by no more than a few percent. INTRODUCTION It has been shown in the past few years that applying a gate-bias stress will shift the threshold-voltage of a SiC MOSFET, and that a subsequent bias of the opposite polarity will cause a shift back in the other direction [1-6]. This VT instability is generally repeatable [2]. Relatively slow I-V measurements, which can take approximately 1 s or longer to complete, reveal threshold-voltage instabilities of around 0.25 to 0.33 V. Much faster I-V measurements reveal a much more significant amount of instability than previously realized, even for short stress times [3, 6]. This result is consistent with charge tunneling into oxide traps distributed spatially in the near-interfacial region, a region that has been shown to include excess carbon and other types of defects [7-9]. A tunneling mechanism would lead to a linear-with-log-time biasstress response such that approximately half of the threshold-voltage instability would occur in the first microsecond for a 1-s bias stress. Likewise, a 1-s ramp-speed measurement will be highly influenced by the bias during the sweep. The faster the ramp speed, the more of the effect of the original bias stress can be observed. Of course, if the measurements are made fast enough the response of interface traps, which vary with energy, will also affect the response. Charge separation analysis suggests that there may be as many as 1×1012 cm-2 oxide traps present [10]. Fast I-V instability measurements suggest that a significant fraction of these traps can act as switching oxide traps [6]. It is important therefore to identify, understand, and reduce these oxide traps, while simultaneously keeping interface traps relatively low. This work shows a direct correlation of the threshold-voltage instability in fully processed 4H-SiC vertical power DMOSFETs with results on lateral SiC MOSFET test structures, in which the instability has been shown to increase as a function of increasing gatebias stress magnitude, gate-bias stre
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