Through-Wafer Polysilicon Interconnect Fabrication with In-Situ Boron Doping
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Through-Wafer Polysilicon Interconnect Fabrication with In-Situ Boron Doping Ismo Luusua1, Kimmo Henttinen1, Panu Pekko1, Tapani Vehmas1, Hannu Luoto1 1 VTT Information Technology, Microelectronics Tietotie 3, FIN-02150 Espoo, Finland
ABSTRACT Bulk micromachining technology can be used to produce conducting through-wafer polysilicon interconnects, i.e., polysilicon via plugs. This paper presents the process fabrication steps of polysilicon via plugs with in-situ boron doped polysilicon material in order to develop fast one-step doping process, without additional diffusion. The via holes can be processed by high-aspect ratio silicon etching with inductively coupled plasma (ICP). Only one deep ICP etching is required if the wafer is mechanically ground (from the backside) to reduce the wafer thickness of 500 microns to a typical of 400, in order to overcome deep etching sidewall profile problems. After hole formation with ICP the via plug fabrication process continues by growing an insulating thermal oxide layer with a thickness of the order of a micron, followed by an in-situ boron doped LPCVD polysilicon growth to fill the holes with sufficient step coverage. The polysilicon growth temperature at 680°C ensures sufficient step coverage, reasonable furnace process time and enables planarization processing, such as grinding and chemical-mechanical polishing (CMP). The subsequent planar processing typically requires planarization of the polysilicon layer down to the original silicon (or oxide) surface with CMP, and some doping activation step, which usually can be performed together with some additional oxidation step. Applications of the via plugs in the field of silicon-based sensors or actuators enable significant reduction of the front surface wiring density, which opens additional space for denser packing or other desired components.
INTRODUCTION Micro electro mechanical systems (MEMS) and various sensors in the planar silicon device technology are an example of potential applications of electrical through-wafer vias. The main purpose of these vias is to reduce space taken by electrical wiring on the active sensor or device area. Polysilicon growth can be performed by the in-situ low pressure chemical vapor deposition (LPCVD), which offers uniform doping through the entire polysilicon layer [1-3]. It should be noted that only boron in-situ doping can be considered for this purpose as phosphorus doping will drastically tend to lower the polysilicon deposition rate [3]. Different polysilicon processing has been employed to produce vertical through-wafer interconnects, especially using double sided ICP etching and polysilicon doping by diffusion [4]. This paper will concentrate on the in-situ boron doping and single sided ICP etching that will produce through-wafer interconnects, or the in-situ boron doped through-wafer vias, with both reasonably low resistance and capacitance.
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Figure 1. Critical steps of the electrical through-wafer via process. Step 1. ICP deep etching, followed by etching of the
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