Use of Porous Silicon to Mnimvize Oxidation Induced Stacking Fault Defects in Silicon
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USE OF POROUS SILICON TO MNIMvIZE OXIDATION INDUCED STACKING FAULT DEFECTS IN SILICON
S.-Y. Shieh and J. W. Evans Materials Science Division, Lawrence Berkeley Laboratory and Department of Materials Science and Mineral Engineering, University of California, Berkeley, CA 94720
ABSTRACT Present methods for minimizing stacking fault defects, generated during oxidation of silicon, include damaging the back of the wafer or depositing poly-silicon on the back. In either case a highly defective structure is created and this is capable of gettering either selfinterstitials or impurities which promote nucleation of stacking fault defects. A novel method of minimizing these defects is to form a patch of porous silicon on the back of the wafer by electrochemical etching. Annealing under inert gas prior to oxidation may then result in the necessary gettering. Experiments were carried out in which wafers were subjected to this treatment. Subsequent to oxidation, the wafers were etched to remove oxide and reveal defects. The regions of the wafer adjacent to the porous silicon patch were defect-free, whereas remote regions had defects. Deep level transient spectroscopy has been used to examine the gettering capability of porous silicon, and the paper discusses the mechanism by which the porous silicon getters.
INTRODUCTION AND PREVIOUS INVESTIGATIONS 1 It has long been recognized that stacking faults, induced during the oxidation steps of integrated circuit manufacturing, are detrimental to circuit performance. Oxidation induced stacking faults (OISF) occur as silicon self-interstitials precipitate within the wafer disturbing the normal stacking sequence of the single crystal. Clusters of transition metal atoms, 5 2 oxygen, or carbon have been suggested as nucleation sites. -4 It has been shown that OISF do not occur uniformly across a wafer but have a higher incidence in a ring that is concentric with the wafer and has a radius dependent on the silicon growth conditions. Various methods have been devised for avoiding OISF. These include the use of chlorine during oxidation, damaging the back of the wafer by abrasion, or ion implantation, and the use of of silicon nitride and polycrystalline silicon on the back of the wafer. The concept behind many of these methods appears to be that a disordered structure on the back side of the wafer can provide gettering centers for either silicon self-interstitials or for impurity atoms. The present paper reports on a novel approach that may be a practical alternative to those listed above, namely the use of porous silicon patches (perhaps on the back of the wafer) as gettering centers. Porous silicon has been the subject of numerous investigations; a computer based search of the literature reveals 270 publications with porous silicon as key words. The material is readily formed by electrochemical oxidation of a silicon wafer in hydrofluoric acid at room 2 2 temperature and current densities in the range 10 mA/cm to 100 mA/cm . Illumination of the surface is necessary for n type silicon bu
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