UV Raman spectroscopy study of strain induced by buried silicon nitride layer in the BOX of Silicon On Insulator substra
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1185-II04-08
UV Raman spectroscopy study of strain induced by buried silicon nitride layer in the BOX of Silicon On Insulator substrates V. Paillard, J. Groenen, P. Puech CNRS-CEMES and Univ. Toulouse, 29 rue Jeanne Marvig, 31055 Toulouse Cedex 4, France Y. Lamrani, M. Kostrzewa, J. Widiez, J.-Ch. Barbé, Ch. Deguet, L. Clavelier CEA-LETI, 17 rue des Martyrs, 38054 Grenoble, France B. Ghyselen Soitec, Parc Technologique des Fontaines, 38926 Crolles Cedex, France ABSTRACT Compressive strained Silicon from a Silicon on Insulator (SOI) substrate is obtained by replacing the buried oxide layer by a strained silicon nitride layer. The silicon overlayer and the buried dielectric are etched down to the substrate to form narrow wires (down to 300 nm wide). The Si overlayer is then expected to acquire compressive strain thanks to the relaxation of the SiN layer. The goal is to obtain a high uniaxial stress perpendicular to the wires. The structures and the strain are modeled using finite element simulations. The strain elements are used to calculate Raman spectra. Theoretical results are compared to experimental profiles deduced from resonant (UV) micro Raman experiments. INTRODUCTION To insure expansion of semiconductor industry, the downscaling of CMOS technology remains the main strategy. For future technology nodes, electrical performance of transistors needs to be improved, for instance by carrier mobility increase. This can be achieved by several techniques that use local and/or global stress engineering in the transistor channel region. This includes strain modulation by using SiGe source and drain, or by depositing strained silicon nitride (SiN) layers over devices [1]. Alternative methods have been studied, such as wafer level introduction of strain, and in particular the use of Strained Silicon On Insulator substrates (Smart CutTM technology applied to transfer of a strained Si layer made by heteroepitaxy on top of a relaxed SiGe template), which benefits from advantages of both SOI and stress engineering [2]. We propose to take advantage of the underneath region of the SOI stack to introduce strain into the active region, by introducing a strained silicon nitride (SiN) layer in the buried oxide (BOX) usually made of pure SiO2. This technique of alter-BOX can be considered either as stand-alone or as an additional method to any of the above-mentioned techniques for channel strain engineering. For this purpose, advanced SOI substrates consisting in a 140 nm thick SiN layer covered by a ultra-thin Si film (about 10 nm) were fabricated. The initial SiN layer is under tensile strain. The silicon overlayer and the buried dielectric are etched down to the substrate to form narrow strips. The overlayer is then expected to acquire compressive strain thanks to the relaxation of the SiN layer. The goal is to obtain a high uniaxial stress perpendicular to the strips.
EXPERIMENTAL AND THEORETICAL DETAILS Fabrication of SOI wafer with buried silicon nitride The substrates with alternative buried dielectric layers are fabricat
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