Multiprocessor System-on-Chip Hardware Design and Tool Integration
Improving future electronic system performance can only be achieved by exploiting parallelism on all system levels. Multicore architectures offer a better performance/Watt ratio than single core architectures with similar performance. Combining multicore
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Michael Hu¨bner
l
Ju¨rgen Becker
Editors
Multiprocessor System-on-Chip Hardware Design and Tool Integration
Editors Michael Hu¨bner Karlsruhe Institute of Technology (KIT) Institut fu¨r Technik der Informationsverarbeitung Vincenz-Prießnitz-Straße 1 76131 Karlsruhe Germany [email protected]
Ju¨rgen Becker Karlsruhe Institute of Technology (KIT) Institut fu¨r Technik der Informationsverarbeitung Vincenz-Prießnitz-Straße 1 76131 Karlsruhe Germany [email protected]
ISBN 978-1-4419-6459-5 e-ISBN 978-1-4419-6460-1 DOI 10.1007/978-1-4419-6460-1 Springer New York Dordrecht Heidelberg London # Springer ScienceþBusiness Media, LLC 2011 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
Preface
For the next decade, Moore’s Law is still going to bring higher transistor densities allowing Billions of transistors to be integrated on a single chip. However, it became more and more obvious that exploiting significant amounts of instructionlevel parallelism with deeper pipelines and more aggressive wide-issue superscalar techniques, and using most of the transistor budget for large on-chip caches has come to an dead end. Especially, scaling performance with higher clock frequencies is getting more and more difficult because of heat dissipation problems and too high energy consumption. The latter is not only a technical problem for mobile systems, but is even going to become a severe problem for computing centers because high energy consumption leads to significant cost factors in the budget. Improving performance can only be achieved by exploiting parallelism on all system levels. Therefore, for high-performance computing systems, for high-end servers as well or for embedded systems, a massive paradigm shift towards multicore architectures is taking place. Integrating multiple cores on a single chip leads to a significant performance improvement without increasing the clock frequency. Multicore architectures offer a better performance/Watt ratio than single core architectures with similar performance. Combining multicore and coprocessor technology promise extreme computing power for highly CPU-time-consuming applications in scientific computing as well as for special purpose applications in the embedded area. Especially FPGAbased accelerators not
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