Why SiN x :H is the Preferred Gate Dielectric for Amorphous Si Thin Film Transistors (TFTS) and SiO 2 is the Preferred G
- PDF / 500,331 Bytes
- 6 Pages / 390.6 x 621.9 pts Page_size
- 5 Downloads / 180 Views
alternative
gate dielectric cde rl c
0 I .... defect scaling -4 ......... N..... (Nav-Nav*)2........................ 2 1.0. i [D] .... ... ............... ....................... ..... . ....................... 0c.80' -*.......
0.5 molecular layer SiO2 interface e. nm m• layer la0.5
0.5 molecular layer Si substrate
0 13
......... ... 0.60 7.. ........
' 0.40 0.20[ ................. .,p .... , ....
m
....... ................. d: SI-Sl3N4(0.4 nm)-SI02
z"0 -02Oorr .. 0.
........ b: SI-SIO2(0.6 nm)-SI3N4 nm)-SI3N4 ... ..... a: SI-SI02(1.5
C: Si-Si3N4
b
0: SI-S13N4(0.8 nm)-Sl02
"a
0.1
0.2
0.3
Over-coordination --
0.4 -Nay N.v*}2
Figure 1. Schematic representation of interface Figure 2. Application of constraint theory to c-Si-dielectric interfaces. Verification of model for application of constraint theory to defect scaling relationship [6]. semiconductor dielectric interfaces 135
Mat. Res. Soc. Symp. Proc. Vol. 558 ©2000 Materials Research Society
0.5
Since total strain energy is proportional to (60)2 [5], it is then anticipated that defect creation, e.g., dangling Si or N bonds, will be proportional to (Nay - Nav*} 2 . ,Experiments have shown that Nav -3 represents a criterion between low defect density (- 1016 cm- 3 ), and increasingly defective materials [4]. A model for the extension of constraint theory to crystalline-Si-dielectric-interfaces is illustrated in Fig I and identifies three interfacial contributions to Nay: i) the Si substrate represented by one-half a Si atom, ii) an ultra thin oxide or nitride interfacial layer (0.5 - 0.6 nm), and iii) the bulk dielectric by one-half a molecular layer [6]. A value of Nay -3, based on the structural model in Fig. 1 is in excellent agreement with experimental data for Si-SiO2, SiSi3N4, and Si-stacked SiO2/Si3N4 and Si3N4/SiO2 interfaces, separating device-quality from highly defective interfaces [6,7]. For example, the model confirms that Si-Si0 2 interfaces are expected to display excellent interface properties (Nag- 2 .8 ), whereas Si-S13N 4 interfaces are not (Nay- 3 .5 ). Equally important, the calculations demonstrate that interposition of ultrathin Si0 2 layers between Si and Si3N 4 results in values of Nay < 3, whereas interposition of ultrathin Si3N4 layers between Si and SiO2 results in Na8 > 3 [6,7J. Figure 2 is based on the data in Ref. 6, and demonstrates that defect scaling for bulk films, Eqn. (1), also holds at interfaces. The situation is somewhat complicated by the nature of the interfacial defects, and in particular their occupancy and charge state in field effect transistor, FET, devices with electron-conducting and hole-conducting channels; i.e., n-channel and p-channel FETs, respectively. For example, experiments performed on n-channel and p-channel FETs with Si-Si3N4 interfaces indicate that the bond-constraint induced defects at interfaces are predominantly donor-like defects in the lower half of the Si band-gap [7). They are neutral when occupied and do not adversely effect channel transport in electron-conducting devic
Data Loading...
