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M8.11.1

Stability of Non-Hydrogenated and Hydrogenated P-Channel Polycrystalline Silicon ThinFilm Transistors N. A. Hastas,1 C. A. Dimitriadis,1 G. Kamarinos 2 1 2

Department of Physics, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece IMEP ENSERG, 23 rue des Martyrs, BP 257, 38016 Grenoble Cedex 1, France

ABSTRACT The effects of high gate voltage Vg stress on the stability of non-hydrogenated and hydrogenated short p-channel polysilicon thin-film transistors (TFTs) are investigated for operation in the saturation region. The degradation mechanisms were identified from the evolution with stress time of the static device parameters. In non-hydrogenated TFTs, transconductance overshoot and a turnover behavior in the threshold voltage were observed. The results indicate that hot-electron trapping near the drain dominates in the initial stages of stress and channel holes are injected into the gate oxide followed by interface states generation as the stress proceeds further. In hydrogenated TFTs, first an effective shortening of the channel length is observed due to trapping of hot-electrons. As the stress proceeds further, donor-type interface states are generated and the electric field near the drain increases due to built-up of positive charge resulted from trapping of hot-holes in these states. INTRODUCTION Polycrystalline silicon thin-film transistors (polysilicon TFTs) are currently investigated due to their applications in liquid crystal display systems on glass with integrated driver and their suitability for three-dimensional integration for high-density SRAM circuit applications [1]. For these applications, polysilicon TFTs are required to have short channel to increase the integration density as well as to drive a large current. Hot-carrier effects in polysilicon TFTs become particularly important as their dimensions are reduced. The instability of the polysilicon TFTs is a more complicated problem compared with the crystalline silicon MOSFETs due to the existence of the grain boundaries and the higher density of in-grain defects. Defect state generation in the polysilicon film, hot-carrier induced interface state generation and charge trapping in the gate insulator are some of the degradation mechanisms responsible for the instability of non-hydrogenated polysilicon TFTs [2, 3]. To improve the TFT performance, hydrogen passivation of the grain boundary and in-grain defects was used for reducing the density of these defect states. However, compared to non-hydrogenated devices, in hydrogenated polysilicon TFTs hot-carrier induced degradation is further enhanced due to breaking of the weak Si-H bonds. In this work, we investigate the main degradation mechanisms of p-channel non-hydrogenated polysilicon TFTs and the effect of hydrogenation on the device stability under the same bias voltages applied during the electrical stress. EXPERIMENTAL DETAILS The devices used throughout this study were fabricated on fused quartz glass substrates, covered by 200 nm thick SiO2 which was deposited by electr